CN1790673A - 集成注入逻辑电路的制造方法 - Google Patents
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Abstract
一种制备I2L电路中的方法,包括(i)在衬底中形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极,公共的横向晶体管的集电极和垂直多集电极晶体管的基极,以及横向晶体管的发射极(10);(ii)由第一淀积多晶层形成共集电极/基极的接触区(7’)和横向晶体管的发射极的接触区(7”);(iii)形成电隔离共集电极/基极的多晶接触区(7’)的隔离结构(8);以及(iv)由第二淀积多晶层形成共基极/发射极的接触区(11’)和垂直多集电极晶体管的多个集电极(11”)。
Description
技术领域
本发明通常涉及集成电路技术领域,更具体地,本发明涉及一种集成注入逻辑电路制造中的方法,并涉及集成注入逻辑电路。
背景技术
BiCMOS技术将双极和CMOS器件结合在单个芯片上。目前已经证明BiCMOS技术对于日益增加的通信(尤其是无线应用)用电路的集成化来说,是非常有用的。由于双极器件广泛用于高频部件,例如用于模拟无线电功能,而CMOS技术用于数字和混合信号部件,例如与系统中其它电路的数据接口。由于高器件密度区域和转换时的低功耗,CMOS技术在逻辑电路方面也具有优势。因此在过去十年,BiCMOS技术一直用于集成度不断增加的与数字模块相连接的基础双极电路模块。
用于无线应用的BiCMOS工艺可以称为高端BiCMOS工艺,在该工艺中蒋CMOS工艺添加到现有的高性能双极工艺中。与将中速双极晶体管添加到高性能CMOS工艺的低端BiCMOS相对照,在性能而非成本方面有优势。Norstr_m等人的美国专利No.6,610,578,以及Johansson等人的国际专利公开WO 02/091463 A1中描述了用于高频无线电应用的高性能双多聚(double-poly)双极工艺,只要对双极工艺进行小的修改就可将这些工艺扩展到BiCOMS。在上述的美国专利中描述了在此工艺中横向PNP晶体管的设计。
集成注入逻辑(I2L或多晶体管逻辑MTL)是于20世纪70年代的早期发明的。该技术提供了高封装密度、低功耗、简单的制造技术、良好的电流驱动能力,并且能在同一晶片很容易地与线形函数和其它逻辑类型相混合。基本的I2L单元包括紧密连接的(超级集成)横向PNP晶体管Q1和垂直多集电极NPN晶体管Q2。这在S.M.Sze(Ed.),“半导体器件物理学”,2nd ed.,Wiley,1981.pp.182-183中的图1a-b中可见。从横向PNP晶体管Q1注入电流到垂直多集电极NPN晶体管Q2的基极。NPN晶体管Q2在反向模式下工作。结果,NPN晶体管的反向β在某些工艺技术中可能太低,使得I2L在不进行工艺改进的情况下无法工作。I2L作为中速技术是非常成功的,当然MOS技术的发展很快降低了它在大的高速数字电路中的重要性,如我们今天拥有的微型处理器。
Sawada在美国专利No.5,504,368中披露了一种电路装置,其中分别形成垂直晶体管以用于NPN高速操作(对双极RF操作有用)和NPN高beta操作(可用于I2L),并形成横向PNP晶体管用于I2L注入极。
Eichler和Wallner的德国专利No.196 14 876讲授了如何将I2L与高电压的NPN晶体管集成的方法。
Yamamoto和Tominaga的美国专利No.5,831,328披露了I2L半导体器件的制造工艺,其中多晶硅集电极接触用于解决金属布线问题。
Chen等人的美国专利No.6,232,193披露了注入逻辑器件,其中场氧化物用于将多个集电极彼此分开。多晶硅用于接触集电极。大量的附加特征更进一步改善了器件。
发明内容
BiCMOS技术的主要劣势是其工艺非常复杂,这导致较高的制造成本和更长的制造周期。
常规的I2L半导体工艺与旧的扩散双极工艺相兼容;然而这一概念并不直接适用于现代的双极工艺技术。
美国专利No.5,504,368披露的器件要求复杂和非常规的制造工艺。此外,该器件似乎没有最佳地使用可利用空间。
因此,本发明的目的是提供一种集成注入逻辑电路制造中的方法,该方法能够克服与前述现有技术相关的问题。
在这一方面,本发明的特殊目的是提供与现代的双极工艺技术相兼容的方法,所述现代双极工艺技术有例如用于制造用于当今的高性能双极和BiCMOS电路的双多聚双极晶体管的方法。
本发明的更进一步的目的是提供这样的方法,其简单易懂并且需要最少的工艺步骤。
本发明还有更进一步的目的是提供这样的方法,通过该方法获得良好的器件隔离。
本发明更进一步的目的是提供这样的方法,用该方法能够制造紧凑且高密度的注入逻辑电路。
本发明更进一步的目的是提供这样的方法,用该方法能够制造包含高性能晶体管的注入逻辑电路。
本发明更进一步的目的是提供在双极工艺中制造包含集成注入逻辑电路和双极放大器器件的无线电收发装置的制造方法。
本发明更进一步的目的是提供一种集成注入逻辑电路,其能够通过实现以上目标的方法制造并包含高性能晶体管。
依照本发明的这些目标通过在所附的专利权利要求中所声明的方法和电路来实现。
根据本发明的一个方面,提供了一种集成注入逻辑电路制造中的方法,该集成注入逻辑电路包含第一掺杂类型的横向双极晶体管和与所述第一掺杂类型相反的第二掺杂类型的垂直双极多集电极晶体管,其中横向双极晶体管的基极与垂直双极多集电极晶体管的发射极是共用的,称为共基极/发射极,并且横向双极晶体管的集电极与垂直双极多集电极晶体管的基极是共用的,称为共集电极/基极。通过离子注入和扩散,将共基极/发射极、共集电极/基极和横向双极晶体管的发射极形成在衬底中。该衬底可以为大块的衬底或绝缘体上硅(SOI)衬底。
第一多晶层被淀积在衬底上并被图形化以形成共集电极/基极的多晶接触区,以及横向双极晶体管的发射极的多晶接触区。淀积隔离层并将其图形化以形成用于共集电极/基极的接触区的电隔离的隔离结构。最后,淀积第二多晶层并将其图形化以形成共基极/发射极的接触区,以及垂直双极多集电极晶体管的多千集电极。
优选地,共集电极/基极形成为通过共集电极/基极的接触区互相连接的多个横向分离区。
在实施例的详细描述中披露了几种布图。其中之一,垂直双极多集电极晶体管的多个集电极被安排在横向双极晶体管的发射极的接触区和共集电极/基极的接触区之间,这沿电路的横向可见。多个集电极被有利地沿一直线布置,该直线与横向的方向实质上垂直。
根据本发明的另一方面,提供了一种制造逻辑电路装置的方法,该逻辑电路装置包含多个集成注入逻辑电路。这种方法在每个集成注入逻辑电路的制造中包括本发明前述方面的方法。
根据本发明的又一方面,提供了一种制造无线电收发装置的方法,该装置包含集成注入逻辑电路和双极放大器器件,其中该方法包括集成注入逻辑电路制造过程中的前述方法。
依照本发明的又一方面,提供一种集成注入逻辑电路,依照集成注入逻辑电路的制造中的上述方法制造该集成注入逻辑电路。
本发明的进一步的特性和优点将从下文给出的本发明的优选实施例的详细描述和附图2-6中得以证实,附图仅以说明的方式给出,因而并不限定本发明。
附图说明
附图1a-b是根据现有技术的集成注入逻辑电路的电路图和高度放大的剖面图。
附图2a是依据本发明实施例的集成注入逻辑电路的示意性布局。图2b-c是沿图2a的电路的A-A线和B-B线的横截面视图。
附图3-5是依据发明另一个实施例的集成注入逻辑电路的示意性布局。
附图6是包括多个如图4布局的集成注入逻辑电路的11级环形震荡器的示意性布局。
在所有附图中相同的参考数字表示相似的部件和部分。
具体实施方式
为了给出对本发明的全面理解,将描述不同的实施例。对本领域技术人员来说,本发明可以以与那些明确披露的实施例不同的实施例来实施是显而易见的。在其他的情况下,省略了本领域技术人员公知方法的详细描述。
应该指出,以下描述的工艺步骤在美国专利No.6,610,578和国际专利公开WO 02/091463A1中有更加详细的描述,在此引入其内容作为参考。尤其是在执行高性能双极晶体管制作的对应工艺步骤时,可以同时执行以下描述的工艺步骤。这样的单独双极工艺(bipolar only process)可用于制作包括放大器结构和逻辑的无线电收发装置。
参照附图2a-c,描述了包括横向双极PNP晶体管和垂直双极NPN多集电极晶体管的单片集成垂直器件的制备中的方法的第一实施例。
如图2b-c所示,提供了p+/p-掺杂的大块衬底晶片1。或者,该晶片是绝缘体上硅(SOI)衬底晶片。
通过离子注入形成文献中常常称为副集电极的掩埋n+掺杂区2。附图2a中以2a表示注入期间界定掩埋n+掺杂区2的掩模布图。如果衬底晶片是SOI衬底晶片,则优选掩埋n+掺杂区2不向下到达绝缘体层。
在掩埋n+掺杂区2的顶部,淀积外延硅层。对此层完成p-掺杂的毯覆式硼注入,从而产生p阱区。进行另外的n-型注入以在该外延层中形成n-掺杂阱区3。n-掺杂阱区3将同时构成横向PNP晶体管的基极和垂直多集电极晶体管的发射极。附图2a中以3a表示界定n-掺杂阱区3的形成的掩模布图。包括其中形成n-掺杂阱区3的外延层的单晶结构通常被称为其中形成了有源部件的衬底。
接着,隔离区4形成于n-掺杂阱区3中。隔离区4可以是LOCOS隔离,浅沟槽隔离(STI)或其它隔离结构。优选地,隔离区4足够浅以便不会向下到达掩埋n+掺杂区2。附图2a中以4a表示用于形成浅隔离区4的掩模布图。
围绕集成注入逻辑电路形成优选为深沟槽的器件隔离结构5,这可以通过附图2a中以5a表示的用于形成器件隔离结构5的掩模布图看出。或者,如果n-阱区3(掩模3a)外部的区域是p阱区,由此产生了器件结构的结隔离。
然后,形成n+掺杂坠(sinker)或接触栓结构6以获得从掩埋n+掺杂区2直至衬底表面的电接触。附图2a中以6a表示形成n+掺杂坠结构6的掩模布图。
在该结构上淀积称为第一多晶层的多晶硅薄层并且随后对其进行p+掺杂。图形化第一多晶层以形成第一、第二多晶接触区7’和7”。附图2a中以7a表示用来形成接触区7’和7”的掩模布图。其上淀积隔离层,从该隔离层形成用来电隔离第一接触区7’的隔离结构8。
在下一步骤中,以低能量向该结构注入p型掺杂剂。在由隔离结构8限定的开口中的衬底中形成p掺杂表面区。后续的热处理使得p型掺杂剂从第一、第二接触区7’和7”扩散至衬底中以形成由第一接触区7’互连的p掺杂区9以及横向PNP晶体管的发射极10。p掺杂区9将同时构成横向PNP晶体管的集电极和垂直多集电极晶体管的基极。
在该结构上淀积第二多晶层并随后对其进行n+掺杂。图形化第二多晶层以形成用于公共的横向PNP晶体管的基极与垂直多集电极晶体管的发射极的多晶接触区11’,并形成垂直多集电极晶体管的多个集电极11”。附图2a中以11a表示用来形成接触区11’和多个集电极11”的掩模布图。
应当理解,在后续热处理期间,n型掺杂剂从多个集电极11”扩散并进入p掺杂区9,以便在衬底表面下获得pn结。
接着,硅化暴露的硅表面以在其上形成薄硅化物层12,之后以传统方式继续进行金属化工艺。
附图2b示出了横向PNP晶体管和垂直多集电极NPN晶体管。它们对应的电流路径通过指向箭头示意性地指出。横向PNP晶体管包括发射极10、基极3及集电极9,并且对应的接触区由7”、11’和7’表示。相似地,垂直多集电极NPN晶体管包括发射极3、基极9及多个集电极11”。发射极和基极的接触区由11’和7’表示,而多个集电极11”经硅化物直接连接至金属。
优选地,多个集电极11”的数目等于p掺杂区9的数目,并且多个集电极11”与p掺杂区9对准,即形成实质上与p掺杂区9交叠的多个集电极11”。
可以在附图2b中看到,垂直多集电极晶体管的多个集电极11”排列在横向晶体管的发射极的接触区7”和公共的横向晶体管的集电极及垂直多集电极晶体管基极的接触区7’之间。
可以在与附图2a有关的附图2c中看到,垂直多集电极晶体管的多个集电极11”基本上沿直线排列,该直线实质上与横向方向正交。
从而上面的方法提供了一种与当今双极工艺技术相兼容的、不需更多工艺步骤的方法,当今的双极技术有例如那些用于制备双多聚双极晶体管的方法。此方法进一步提供了具有高性能晶体管的、紧凑且高密度的注入逻辑的制造。
假如在制备高性能双极晶体管的工艺中实施上面的方法,在形成公共的横向PNP晶体管的基极和垂直NPN多集电极晶体管的发射极的同时,在衬底中形成高性能双极晶体管的集电极。在形成公共的横向PNP晶体管的集电极和垂直NPN多集电极晶体管的基极的接触区7’以及横向PNP晶体管的发射极的接触区7”的同时,由第一多晶层形成高性能双极晶体管的基极接触区。在形成公共的横向PNP晶体管的基极和垂直NPN多集电极晶体管的发射极的多晶接触区11’以及垂直NPN多集电极晶体管的多个集电极11”的同时,由第二多晶层形成高性能双极晶体管的发射极接触区。
附图3-6示出了发明的更多实施例的示意布图。可以使用没有修改的上述工艺,仅是布图有区别。
在附图3示出的实施例中,公共的横向PNP晶体管的集电极和垂直NPN多集电极晶体管的基极的多晶接触区7’与垂直NPN多集电极晶体管的多个集电极11”一同沿一直线排列。这可以通过附图3中用于淀积的第一、第二多晶层7a和11a的掩模布图看出。
在附图4示出的实施例中,横向PNP晶体管发射极的接触区7’与垂直NPN多集电极晶体管的八个集电极11”一同沿一直线排列。这可以通过附图4中用于淀积的第一、第二多晶层7a和11a的掩模布图看出。
在附图5示出的实施例中,垂直NPN多集电极晶体管的八个集电极11”基本上沿两条平行直线排列,并且横向PNP晶体管发射极的接触区7”以及公共的横向PNP晶体管的集电极和垂直NPN多集电极晶体管的基极的接触区7’沿两条平行直线延长和排列,垂直双极多集电极晶体管的八个集电极也沿上述直线排列。这可以通过附图5中用于淀积的第一、第二多晶层7a和11a的掩模布图看出。
在附图6示出的实施例中,示出了包括六个均为附图4中示出的集成注入逻辑电路71的11级环形震荡器。器件隔离结构72,尤其是深沟槽,围绕六个集成注入逻辑电路的每一个形成。注意,由于每两个相邻的集成注入逻辑电路71共享一直沟槽结构,从而得到紧凑的结构。
如此描述的本发明可以用作各种各样的逻辑电路装置的制造,尤其是与高性能RF双极器件结合。
Claims (21)
1.一种集成注入逻辑电路制造中的方法,该集成注入逻辑电路包括第一掺杂类型的横向双极晶体管和与所述第一掺杂类型相反的第二掺杂类型的垂直双极多集电极晶体管,其中横向双极晶体管的基极(3)与垂直双极多集电极晶体管的发射极(3)是共用的,且横向双极晶体管的集电极(9)与垂直双极多集电极晶体管的基极(9)是共用的,该方法的特征在于以下步骤:
-在衬底中形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极、公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极、以及横向双极晶体管的发射极(10),
-在衬底上淀积第一多晶层,并由该第一多晶层形成公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’);以及横向双极晶体管的发射极的多晶接触区(7”),
-淀积隔离层,并由该隔离层形成用于电隔离公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’)的隔离结构(8),以及
-淀积第二多晶层,并由该第二多晶层形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极的多晶接触区(11’);以及垂直双极多集电极晶体管的多个集电极(11”)。
2.权利要求1的方法,其中公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极形成为多个横向分开的区域(9),这些区域(9)通过公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’)互连。
3.权利要求2的方法,其中所述多个横向分开的区域(9)的数量等于垂直双极多集电极晶体管的多个集电极(11”)的数量。
4.权利要求1-3中任一项的方法,其中垂直双极多集电极晶体管的多个集电极(11”)设置在横向双极晶体管的发射极的接触区(7”)与公共的横向双极晶体管的集电极及垂直双极多集电极晶体管的基极的多晶接触区之间,这在所述电路的横向方向(A-A)可看到。
5.权利要求4的方法,其中垂直双极多集电极晶体管的多个集电极(11”)基本上沿直线(B-B)排列,该直线(B-B)实质上与所述横向方向垂直。
6.权利要求1-3中任一项的方法,其中垂直双极多集电极晶体管的多个集电极(11”)基本上沿一直线排列,并且横向双极晶体管发射极的接触区(7”)、或公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’)与垂直双极多集电极晶体管的多个集电极一起沿该直线排列。
7.权利要求1-3中任一项的方法,其中垂直双极多集电极晶体管的多个集电极(11”)基本上沿两条平行直线排列,并且横向双极晶体管的发射极的接触区(7”)、和公共的横向双极晶体管的集电极及垂直双极多集电极晶体管的基极的多晶接触区(7’)沿这两条平行直线平行延长和排列,垂直双极多集电极晶体管的多个集电极基本沿上述直线排列。
8.权利要求1-7中任一项的方法,其中隔离结构(5),尤其是深沟槽,围绕所述集成注入逻辑电路形成。
9.权利要求1-8中任一项的方法,其中在大块衬底中形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极、公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极、以及横向双极晶体管的发射极。
10.权利要求1-8中任一项的方法,其中在SOI衬底中形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极、公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极、以及横向双极晶体管的发射极。
11.权利要求1-10中任一项的方法,其中所述方法在单独双极工艺中实施。
12.一种制造包含多个集成注入逻辑电路(71)的逻辑电路装置的方法,所述方法在该多个集成注入逻辑电路中每一个的制造中包括权利要求1-11中任一项的方法。
13.权利要求12的方法,其中其中隔离结构(72),尤其是深沟槽,围绕该多个集成注入逻辑电路中的每一个形成。
14.一种制造包含集成注入逻辑电路的无线电收发装置的方法,所述方法包括权利要求1-11中任一项的方法。
15.权利要求14的方法,其中无线电收发装置包含双极放大器器件,并且所述方法包括在单个管芯上同时制造所述集成注入逻辑电路和所述双极放大器器件。
16.权利要求15的方法,其中在形成公共的横向双极晶体管的基极(3)和垂直双极多集电极晶体管的发射极(3)的同时,在所述衬底中形成所述双极放大器器件的集电极。
17.权利要求15或16的方法,其中在形成公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’)以及横向双极晶体管的发射极的多晶接触区(7”)的同时,由第一多晶层形成所述双极放大器器件的基极接触区。
18.权利要求15-17中任一项的方法,其中在形成公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极的多晶接触区(11’)以及垂直双极多集电极晶体管的多个集电极(11”)的同时,由第二多晶层形成所述双极放大器器件的发射极接触区。
19.一种集成注入逻辑电路,包括第一掺杂类型的横向双极晶体管和与所述第一掺杂类型相反的第二掺杂类型的垂直双极多集电极晶体管,其中横向双极晶体管的基极(3)与垂直双极多集电极晶体管的发射极(3)是共用的,且横向双极晶体管的集电极(9)与垂直双极多集电极晶体管的基极(9)是共用的,其特征在于:
-在衬底中提供公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极、公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极、以及横向双极晶体管的发射极(10),
-在所述衬底上提供公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’);以及横向双极晶体管的发射极的多晶接触区(7”),
-提供隔离结构(8),其用于电隔离公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’),以及
-在所述衬底上提供公共的横向双极晶体管的基极和垂直双极多集电极晶体管的发射极的多晶接触区(11’);以及垂直双极多集电极晶体管的多个集电极(11”)。
20.权利要求19的电路,其中公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极形成为多个横向分开的区域(9),这些区域(9)通过公共的横向双极晶体管的集电极和垂直双极多集电极晶体管的基极的多晶接触区(7’)互连。
21.一种无线电收发装置,包括单个管芯上的双极放大器器件和权利要求19或20的集成注入逻辑电路。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101887911A (zh) * | 2009-05-12 | 2010-11-17 | 联发科技股份有限公司 | 横向双极结型晶体管及其制造方法 |
CN102244078A (zh) * | 2011-07-28 | 2011-11-16 | 启东市捷捷微电子有限公司 | 台面工艺可控硅芯片结构和实施方法 |
CN108878367A (zh) * | 2017-05-09 | 2018-11-23 | 上海珏芯光电科技有限公司 | BiCMOS集成电路器件的制造方法及器件 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7875513B2 (en) * | 2006-04-26 | 2011-01-25 | Fabio Pellizzer | Self-aligned bipolar junction transistors |
JP2007299890A (ja) * | 2006-04-28 | 2007-11-15 | Fujitsu Ltd | 半導体装置の製造方法 |
US9030867B2 (en) * | 2008-10-20 | 2015-05-12 | Seagate Technology Llc | Bipolar CMOS select device for resistive sense memory |
US8674454B2 (en) | 2009-02-20 | 2014-03-18 | Mediatek Inc. | Lateral bipolar junction transistor |
US8159856B2 (en) * | 2009-07-07 | 2012-04-17 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
CN102097464B (zh) * | 2009-12-15 | 2012-10-03 | 上海华虹Nec电子有限公司 | 高压双极晶体管 |
CN102117827B (zh) * | 2009-12-31 | 2012-11-07 | 上海华虹Nec电子有限公司 | BiCMOS工艺中的寄生垂直型PNP器件 |
US8648426B2 (en) | 2010-12-17 | 2014-02-11 | Seagate Technology Llc | Tunneling transistors |
CN102522425B (zh) * | 2011-12-23 | 2014-04-16 | 上海华虹宏力半导体制造有限公司 | 超高压锗硅hbt晶体管器件的结构及制备方法 |
CA2970174C (en) * | 2014-12-08 | 2024-01-23 | Berkeley Lights, Inc. | Microfluidic device comprising lateral/vertical transistor structures and process of making and using same |
CN114093937B (zh) * | 2021-11-25 | 2023-08-22 | 中国电子科技集团公司第二十四研究所 | 一种双极晶体管及其制备方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1485970A (en) | 1974-10-01 | 1977-09-14 | Texas Instruments Ltd | Integrated injection logic circuit structure |
JPS559464A (en) | 1978-07-07 | 1980-01-23 | Toshiba Corp | Production method of bipolar integrated circuit containing i2 l |
US4512075A (en) * | 1980-08-04 | 1985-04-23 | Fairchild Camera & Instrument Corporation | Method of making an integrated injection logic cell having self-aligned collector and base reduced resistance utilizing selective diffusion from polycrystalline regions |
KR950011017B1 (ko) * | 1991-07-01 | 1995-09-27 | 미쯔시다덴기산교 가부시기가이샤 | 반도체장치 및 그 제조방법 |
DE69232348T2 (de) | 1991-09-24 | 2002-08-14 | Matsushita Electric Ind Co Ltd | Integrierte Halbleiterschaltungsanordnung und Verfahren zu ihrer Herstellung |
JPH08213475A (ja) | 1995-02-07 | 1996-08-20 | Mitsubishi Electric Corp | 半導体装置とその製造方法 |
JP3489265B2 (ja) * | 1995-05-19 | 2004-01-19 | ソニー株式会社 | 半導体装置の製法 |
DE19614876C1 (de) | 1996-04-16 | 1997-11-13 | Telefunken Microelectron | Verfahren zur Herstellung einer integrierten Halbleiteranordnung mit I·2·L-Logikinvertern in Kombination mit hochsperrenden NPN-Transistoren |
KR100258436B1 (ko) * | 1996-10-11 | 2000-06-01 | 김덕중 | 상보형 쌍극성 트랜지스터 및 그 제조 방법 |
CN1179627A (zh) * | 1996-10-11 | 1998-04-22 | 三星电子株式会社 | 互补双极晶体管及其制造方法 |
CA2295990A1 (en) | 1997-07-11 | 1999-01-21 | Telefonaktiebolaget Lm Ericsson | A process for manufacturing ic-components to be used at radio frequencies |
US6140694A (en) | 1998-12-30 | 2000-10-31 | Philips Electronics North America Corporation | Field isolated integrated injection logic gate |
US6332193B1 (en) * | 1999-01-18 | 2001-12-18 | Sensar, Inc. | Method and apparatus for securely transmitting and authenticating biometric data over a network |
JP2001217317A (ja) * | 2000-02-07 | 2001-08-10 | Sony Corp | 半導体装置およびその製造方法 |
SE0103036D0 (sv) | 2001-05-04 | 2001-09-13 | Ericsson Telefon Ab L M | Semiconductor process and integrated circuit |
-
2004
- 2004-10-06 EP EP04023839A patent/EP1646084A1/en not_active Withdrawn
-
2005
- 2005-09-30 CN CNB200510119987XA patent/CN100435319C/zh not_active Expired - Fee Related
- 2005-10-06 US US11/245,469 patent/US7456069B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101887911A (zh) * | 2009-05-12 | 2010-11-17 | 联发科技股份有限公司 | 横向双极结型晶体管及其制造方法 |
CN102244078A (zh) * | 2011-07-28 | 2011-11-16 | 启东市捷捷微电子有限公司 | 台面工艺可控硅芯片结构和实施方法 |
CN102244078B (zh) * | 2011-07-28 | 2013-06-12 | 江苏捷捷微电子股份有限公司 | 台面工艺可控硅芯片结构和实施方法 |
CN108878367A (zh) * | 2017-05-09 | 2018-11-23 | 上海珏芯光电科技有限公司 | BiCMOS集成电路器件的制造方法及器件 |
Also Published As
Publication number | Publication date |
---|---|
CN100435319C (zh) | 2008-11-19 |
US7456069B2 (en) | 2008-11-25 |
US20060105517A1 (en) | 2006-05-18 |
EP1646084A1 (en) | 2006-04-12 |
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