IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 11, NOVEMBER 2014 5811 Analytical Method for Pattern Generation in Five-Level Cascaded H-Bridge Inverter Using Selective Harmonic Elimination Concettina Buccella, Senior Member, IEEE, Carlo Cecati, Fellow, IEEE, Maria Gabriella Cimoroni, and Kaveh Razi Abstract—This paper proposes an analytical procedure for computation of all pairs of valid switching angles used in pattern generation in five-level H-bridge cascaded inverters. The proposed procedure eliminates harmonic components from inverter output voltage and, for each harmonic, returns the exact boundaries of all valid modulation index intervals. Due to its simple mathematical formulation, it can be easily implemented in real time using a digital signal processor or a field-programmable gate array. In this paper, after a detailed description of the method, simulation and experimental results demonstrate the high quality of achievable results. Index Terms—Cascaded multilevel inverters, Chebyshev polynomials, high-power converters, modulation, selective harmonic elimination (SHE), total harmonic distortion (THD), Waring formulas. I. I NTRODUCTION S ELECTIVE harmonic elimination (SHE) methods, originated by the harmonic elimination technique early proposed by Patel for high-power inverters, offer enhanced operations at low switching frequency while reducing size and cost of bulky passive filters [1], [2]. They have been successful adopted in different converter topologies, including cascaded H-bridge multilevel converters, whose N -level ac voltage outputs already improve the total harmonic distortion (THD) [3]–[11]. SHE equations are nonlinear; moreover, simple, multiple, or even no solutions could be accomplished for each modulation index [11]. Moreover, it is necessary to know how to obtain all possible sets of solutions and where they exist [12], [13]. Once a set has been obtained, some selection criteria should be adopted. For instance, the lowest THD could be early identified and then selected [14]; another possible criterion could be minimization of mutations in solution sets [15], [16]. Manuscript received July 1, 2013; revised November 26, 2013; accepted January 25, 2014. Date of publication February 25, 2014; date of current version June 6, 2014. This work was supported by DigiPower Ltd., L’Aquila, Italy. C. Buccella, C. Cecati, and K. Razi are with the Department of Information Engineering, Computer Science, and Mathematics, University of L’Aquila, 67100 L’Aquila, Italy; and also with DigiPower Ltd., 67100 L’Aquila, Italy (e-mail: concettina.buccella@univaq.it; carlo.cecati@univaq.it; kaveh.razi@univaq.it). M. G. Cimoroni is with the Department of Information Engineering, Computer Science, and Mathematics, University of L’Aquila, 67100 L’Aquila, Italy (e-mail: mariagabriella.cimoroni@univaq.it). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2014.2308163 Many authors dealt with the SHE problem. The authors in [17]–[21] proposed iterative numerical techniques. The authors in [22] proposed a generalized formulation for half-cycle symmetry SHE–pulsewidth-modulation problems in multilevel inverters, solving the equations by using a Matlab function (fsolve). Authors in [20] proposed a harmonic suppression technique for double-cell inverters called “mirror surplus harmonic method” and using an unconstrained optimization, and in [23], the Walsh function-based analytical technique is adopted, where the harmonic amplitude is expressed directly as a function of switching angles, the latter obtained solving linear algebraic equations rather than nonlinear transcendental equations. In [24] and [25], theories of resultants and of symmetric polynomials were used to characterize, for each modulation index, the existence of the solution and then to solve polynomial equations obtained from transcendental equations. Many authors use genetic algorithms (GAs) ([26]–[28]). In [29], the bee algorithm is applied and compared with a GA; in [30] and [31], a solution has been obtained by using particle swarm optimization (PSO). Paper [32] proposes a PSO-algorithm-based staircase modulation strategy for modular multilevel converters. Bacterial foraging algorithm and ant colony method were adopted in [33] and [34], respectively. Another approach, based on homotopy and continuation theory, was proposed in [35]–[37] for determination of one set of solutions. Minimization techniques were proposed in [38] and [39]. The main drawbacks of existing SHE methods are their mathematical complexity and the heavy computational loads, resulting high cost of the hardware needed for real-time implementation [10]. The last problem is commonly circumvented by preliminary off-line computation of the switching angles and the subsequent creation of lookup tables to be stored in the microcontroller’s internal memory for real-time fetching. This approach, even if effective, in some cases could lead to some drawbacks, particularly the use of discrete modulation indices, resulting in nonoptimum commutations and the need of significant amounts of the microcontroller’s memory. Some requirements cannot be fulfilled by current microcontrollers/DSPs specifically designed for energy management and motion control [the so-called digital signal controllers (DSCs)], due to their limited amount of RAM and the relatively high speed of their internal FLASH memory [42], [43]. Moreover, implementation of feedback control requires distinct lookup tables for each modulation index and limits achievable 0278-0046 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. 5812 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 11, NOVEMBER 2014 Fig. 1. Three-phase five-level cascaded inverter. (a) Schematic diagram of a three-phase five-level cascaded inverter. (b) (A) Phase A and [(B) and (C)] individual H-Bridge output waveforms. performance and/or introduces programming complexity and/or potential problems in closed-loop systems. This paper considers five-level cascaded H-bridge inverters and proposes a procedure allowing fully analytical calculation (i.e., without any lookup table) of those switching angles α1 and α2 , eliminating one harmonic hi (i = 3, 5, 7, . . .). The procedure uses Chebyshev polynomials and Waring formulas [40], [41] and, due to its limited complexity, can be easily implemented in real time using DSC, programmable logic device, or field-programmable gate array (FPGA) [42]. Moreover, it is almost general and can be extended to different topologies and, for the considered topology, to higher number of levels. Specific sets of equations have to be determined for each case. The proposed method can be implemented both off-line and online, i.e., in real time. Its most important advantages are the possibility to obtain exact solution in real time and that it is possible to obtain all possible solutions. The described features are very useful in implementation of closed-loop control and, due to limited algorithm complexity, do not require specific hardware [44]. In the following, Section II deals with problem formulation, Section III describes the determination of modulation index interval, and Section IV describes the procedure for the determination of switching angles. Section V shows some simulation results and deals with some analysis, while Section VI reports experimental results and their comparison with simulations. Good agreement is noted among experimental and simulation results, confirming the accuracy of the proposed technique. Finally, Section VII draws some conclusions. where α1 and α2 are the switching angles necessary for modulation. Fig. 1(b) also shows modulation signals (b) and (c), which are necessary for obtaining the desired output waveform vAN (ωt). The following condition has to be verified: 0 ≤ α1 ≤ α2 ≤ π/2. (2) In order to eliminate a specific harmonic, the following condition must be imposed to find out the unknown switching angles α1 and α2 : F (α) = 0 where F = (F1 , F2 ) and α = (α1 , α2 ) yield  F1 (α1 , α2 ) = cos(α1 ) + cos(α2 ) − 2m1 F2 (α1 , α2 ) = cos(kα1 ) + cos(kα2 ) (3) (4) and k = 3, 5, 7, . . . is the harmonic order to be eliminated. As shown in (4), the first equation in (3) is used to control the magnitude of the fundamental voltage, while the second one is used for harmonic order elimination. It is worth noticing from (4) that the number of equations corresponds to the number of existing H-bridges. The term m1 represents the modulation index defined as m1 = V1 /V1 max , where V1 is the fundamental output peak voltage and V1 max is the maximum obtainable fundamental peak voltage expressed as V1 max = 8Vdc /π. III. S EARCH OF M ODULATION I NDEX I NTERVALS II. M ODEL D ESCRIPTION A three-phase five-level cascaded inverter is considered. Its basic schematic diagram is shown in Fig. 1(a). Each phase consists of two H-bridges fed by separate and balanced dc sources vA1 = vA2 = Vdc . Considering, for instance, phase A multilevel voltage: vAN = vA1 + vA2 , its Fourier series expansion resultsthe following [45]: 4Vdc  vAN (ωt) = [cos(nα1 ) + cos(nα2 )] sin(nωt)/n π n n = 1, 3, 5, 7, . . . (1) Odd Chebyshev polynomials of first type Tk are introduced for the previously described problem and defined by recursive relationship [40] ⎧ ⎨ T0 (x) = 1 T1 (x) = x (5) ⎩ Tj+1 (x) = 2xTj (x) − Tj−1 (x) or Tj (x) = cos(j arccos(x)), j = 1, 2, . . .. The expressions Tk (x) for k = 3, 5, 7, 9, 11, respectively, are described in the Appendix. BUCCELLA et al.: ANALYTICAL METHOD FOR PATTERN GENERATION IN H-BRIDGE INVERTER USING SHE 5813 Similar considerations arise with any other harmonic. Fig. 4 shows valid modulation index intervals given by Theorem 1 at different k values (rows) and subintervals where different m1 ’s produce a different number of valid solutions Nk (m1 ). In the same figure, the ends of each subinterval are highlighted, and each dot within an interval represents a valid solution. The graphs in Fig. 5 represent the functions Nk (m1 ), k = 3, 5, 7, 9, 11. Notice that the maximum number of solutions in a subinterval for each m1 is (k − 1)/2 for k = 3, 5, and it is (k − 3)/2 for k = 7, 9, 11; hence, it is possible to know the number of solutions achieving the kth harmonic elimination (k = 3, 5, . . . , ). IV. D ETERMINATION OF S WITCHING A NGLES Fig. 2. Graphical analysis for the third-harmonic elimination. By substitution of Chebyshev polynomials in (3), the following polynomial system is obtained:  T1 (x1 ) + T1 (x2 ) − 2m1 = 0 (6) Tk (x1 ) + Tk (x2 ) = 0 where x1 = cos(α1 ), x2 = cos(α2 ), and k = 3, 5, 7, . . .. Proposition 1: Let D = [0, 1] × [0, 1], zi = cos(((2i − 1)/2k)π), i = 1, . . . , (k − 1)/2, i.e., all positive zeros of the Chebyshev polynomial Tk (x) with k = 2l + 1, l ≥ 1. 1) If m1 = zi /2, i = 1, . . . , (k − 1)/2, the points (0, zi ) and (zi , 0) are solutions of the system (6) in D. 2) If m1 = zi , i = 1, . . . , (k − 1)/2, the points (zi , zi ) are solutions of the following system:  x + x − 2m = 0 1 2 1 x1 − x2 = 0 Tk (x1 ) + Tk (x2 ) = 0 (7) in D. To better clarify the previous proposition, Figs. 2 and 3(d) show the graphical representation of (7). The straight line x1 + x2 − 2m1 = 0 is drawn at m1 = zi /2 and m1 = zi , i = 1, . . . , (k − 1)/2, for k = 3, 5, 7, 9, 11, respectively. Theorem 1: The system (6) has real solutions in D if and only if m1 ∈ [(1/2) cos(((k − 2)/2k)π), cos(π/2k)] ⊂ [0, 1]. Figs. 2 and 3 show the whole set of solutions for (6) in D within different subintervals of modulation index m1 . Considering, for instance, Fig. 3(a), the straight line x1 + x2 = 2m1 obtained for the following. 1) z2 /2 ≤ m1 < z1 /2 intersects the curve T5 (x1 ) + x1 , x 2 ) T5 (x2 ) = 0 in two distinct symmetrical points ( and ( x2 , x 1 ), representing a unique solution (for the symmetry) for the electrical problem; 2) z1 /2 ≤ m1 ≤ z2 intersects the curve T5 (x1 ) + T5 (x2 ) = 0 in four distinct symmetrical points, representing two solutions for the electrical problem; 3) z2 < m1 ≤ z1 intersects the curve T5 (x1 ) + T5 (x2 ) = 0 in two distinct symmetrical points, representing a unique solution for the electrical problem. In order to explain the method in a simple way and without any loss of generality, in this paper, eliminations of third, fifth, and seventh harmonics are considered. From (6), by applying the Chebyshev polynomials (see the Appendix), the following systems are obtained. 1) k = 3  x1 + x2 = 2m1 (8) 4 x3 + x3 − 3(x + x ) = 0. 1 2 1 2 2) k = 5  x1 + x2 = 2m1 16 x51 + x52 − 20 x31 + x32 + 5(x1 + x2 ) = 0. 3) k = 7  x + x = 2m 1 2 1 64 x71 + x72 − 112 x51 + x52 + 56 x31 + x32 + −7(x1 + x2 ) = 0. (9) (10) Assuming that s = x1 + x2 and p = x1 x2 and applying Waring’s formula (see the Appendix) to previous systems, for each harmonic, the following equations in p with degree l = (k − 1)/2 can be obtained, respectively, with s = 2m1 . 1) k = 3 12p − (4s2 − 3) = 0. (11) 2) k = 5 80p2 + 20(3 − 4s2 )p + (16s4 − 20s2 + 5) = 0. (12) 3) k = 7 448p3 − 112(8s2 − 5)p2 + 56(8s4 − 10s2 + 3)p + − (64s6 − 112s4 + 56s2 − 7) = 0. (13) In the following, the acceptability of each solution for previous equations is investigated. In order to guarantee real solutions (x1 , x2 ) ∈ [0, 1] × [0, 1], for each valid modulation index, the following condition must be verified: 0 ≤ p ≤ m21 . (14) 5814 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 11, NOVEMBER 2014 Fig. 3. Graphical analysis for the harmonic elimination. (a) Fifth harmonic. (b) Seventh harmonic. (c) Ninth harmonic. (d) Eleventh harmonic. Fig. 4. Valid modulation index intervals to vary harmonic order k to eliminate. Fig. 5. Valid modulation index intervals with the solution (switching angle) number.  x1 + x2 = 2m1 is solved evaluating zeros of x1 x2 = p function P2 (ξ) = ξ 2 − sξ + p; hence, the modulator’s angles α1 and α2 are computed by using inverse cosine function. Notice that, regarding (14) with m1 given by Theorem 1, condition p ≤ m21 is obtained, imposing discriminant s2 − 4p ≥ 0 to solutions of ξ 2 − sξ + p = 0. It is worth noticing in Figs. 2 and 3 that a relationship between m1 and (α1 , α2 ) holds at the borders of each modulation index subinterval: when m1 = zi , it follows that (α1 , α2 ) = [arccos(zi ), arccos(zi )], and when m1 = zi /2, it follows that (α1 , α2 ) = [arccos(zi ), π/2]. Table I summarizes this relationship for the case shown in Fig. 3(a). The system TABLE I R ELATIONSHIP B ETWEEN m1 AND (α1 , α2 ) FOR THE F IFTH -H ARMONIC E LIMINATION V. S IMULATION R ESULTS The proposed modulation technique was preliminarily verified by means of simulations and then implemented using a BUCCELLA et al.: ANALYTICAL METHOD FOR PATTERN GENERATION IN H-BRIDGE INVERTER USING SHE 5815 Fig. 6. Examples of harmonic elimination. (a) Output phase voltage. (b) FFT analysis. (c) Third-harmonic elimination (m1 = 0.8). (d) Output phase voltage. (e) FFT analysis. (f) Fifth-harmonic elimination (m1 = 0.9). (g) Output phase voltage. (h) FFT analysis. (i) Seventh-harmonic elimination (m1 = 0.8). TABLE II S WITCHING A NGLE VALUES Fig. 8. Functional block diagram. of high power; therefore, simulations were carried out choosing a setup operating at medium voltage (Vdc = 3 kV) and with rated power equal to 300 kVA. Load was simulated by an R − L network consisting of a set of resistances R = 108 Ω in series with inductances L = 15 mH. Output phase voltage and corresponding fast Fourier transformation (FFT) spectrum are shown in Fig. 6(a), (d), and (g) for the third-, fifth-, and seventh-harmonic eliminations and modulation index equal to m1 = 0.8, m1 = 0.9, and m1 = 0.8, respectively. It can be noticed that, in all cases, the desired harmonic is eliminated. Table II shows the values of the switching angles returned by the third-, fifth-, and seventh-harmonic eliminations at different modulation indices. VI. E XPERIMENTAL R ESULTS Fig. 7. Cascaded H-bridge five-level single-phase inverter prototype. low-power laboratory prototype. A complete converter with load was modeled using Matlab/Simulink [46]. SHE is typical Because of laboratory restrictions, a low-power single-phase five-level cascaded H-bridge inverter was developed for experimental verification and is shown in Fig. 7. The prototype developed by DigiPower Ltd. consists of control and 5816 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 11, NOVEMBER 2014 Fig. 9. Experimental results: output voltage and corresponding FFT, third-harmonic elimination. (a) m1 = 0.45. (b) m1 = 0.8. Fig. 10. Experimental results: output voltage and corresponding FFT, fifth-harmonic elimination. (a) m1 = 0.6. (b) m1 = 0.9. Fig. 11. Experimental results: output voltage and corresponding FFT, seventh-harmonic elimination. (a) m1 = 0.45. (b) m1 = 0.8. power units. The control board includes a microcontroller Atmel ATmega16, as shown in Fig. 8, providing the user’s interface and a Xilinx Spartan II XC2S50 FPGA, in charge of pulse generation and dead-band logics with 16-b resolution, corresponding to ±0.002◦ accuracy [47], [48]. Communications between FPGA and microcontroller are through the Serial Peripheral Interface protocol. The main functional block diagram shown in Fig. 8 summarizes the main operations. To practically demonstrate the achievable performance, six separate experiments with different modulation indices for the elimination of the third, fifth, and seventh harmonics were performed, and results are shown in Figs. 9–11. In these figures, the output voltage and fundamental frequency are VP P = 80 V and f = 50 Hz, respectively (top subfigures), while the base scales for FTT analysis are 5 Vrms /div and f = 100 Hz/div (bottom subfigures). In detail, Fig. 9(a) deals with the third-harmonic elimination in the case of modulation index m1 = 0.45, BUCCELLA et al.: ANALYTICAL METHOD FOR PATTERN GENERATION IN H-BRIDGE INVERTER USING SHE Fig. 10(a) and (b) deals with the fifth-harmonic elimination at different modulation indices (m1 = 0.6 or m1 = 0.9), and Fig. 11(a) and (b) deals with the seventh-harmonic elimination at modulation indices m1 = 0.45 and m1 = 0.80, respectively. FFT analysis clearly shows a complete elimination of undesired harmonics by inverter output voltage. Previous experiments confirm simulation results demonstrating the quality of the approach and its independence by modulation index, which can vary with continuity, thus allowing successful implementation in feedback control loops. This result is very useful as it leads to significant enhancements and advantages over lookup-table-based methods. It is worth noticing that, because of limited algorithm complexity, the same microprocessor or FPGA could be used for implementation of closed-loop control algorithm and other functions; moreover, the memory demand is affordable. Therefore, a typical implementation requires system-on-chip solutions. Another important advantage is the knowledge of the exact values of the modulation angles, which is not given by any other method. VII. C ONCLUSION In this paper, the problem of harmonic elimination in multilevel converters has been addressed considering a five-level cascaded H-bridge inverter and proposing a new analytical algorithm for the computation of the switching angles α1 and α2 capable of elimination of harmonic signals. Since, in order to obtain these angles, it is necessary to find all valid intervals of the modulation index for which they exist, a new analytical procedure has been proposed, which returns the desired intervals split into subintervals and dependent on the number of pairs of switching angles capable of elimination of the selected harmonic. As an example, procedures for obtaining correct switching angles for third-, fifth-, and seventh-harmonic eliminations have been shown. The obtained simulation and experimental results confirm the accuracy of the proposed procedure. Work is in progress in order to extend the method to multiple harmonic elimination and to take into account multilevel voltage imbalances. A PPENDIX The Tk (x) expressions, k = 3, . . . , 11, are as follows. 1) 2) 3) 4) 5) T3 (x) = 4x3 − 3x. T5 (x) = 16x5 − 20x3 + 5x. T7 (x) = 64x7 − 112x5 + 56x3 − 7x. T9 (x) = 256x9 − 576x7 + 432x5 − 120x3 + 9x. T11 (x) =1024x11 − 2816x9 + 2816x7 − 1232x5 + 220x3 − 11x. Proof of Proposition 1 The straight line x1 + x2 = 2m1 with m1 = zi /2, i = 1, . . . , (k − 1)/2, intersects boundaries x1 = 0 and x2 = 0 of D in (zi , 0) and (0, zi ) for i = 1, . . . , (k − 1)/2. These points (zi , 0) and (0, zi ) are also solutions of the equation Tk (x1 ) + Tk (x2 ) = 0. If (x1 , x2 ) ∈ D, it is easy to verify that 5817 the intersection of curve Tk (x1 ) + Tk (x2 ) = 0 with straight line x1 − x2 = 0 is the point (zi , zi ) satisfying also equation x1 + x2 − 2zi = 0. Proof of Theorem 1 Considering that min {zi } = z(k−1)/2 = cos(((k − 1≤i≤(k−1)/2 2)/2k)π) and max1≤i≤(k−1)/2 {zi } = z1 = cos(π/2k), by Proposition 1 and graphical analysis results, the thesis follows. The Waring formulas for the considered harmonics with s = x1 + x2 and p = x1 x2 are as follows: x31 + x32 = s3 − 3ps x51 + x52 = s5 − 5ps3 + 5p2 s x71 + x72 = s7 − 7ps5 + 14p2 s3 − 7p3 s. (15) (16) (17) ACKNOWLEDGMENT The authors would like to thank Mr. F. Mancini, University of L’Aquila, for his assistance during laboratory activity, and the anonymous Associate Editor and Reviewers for their insightful comments. R EFERENCES [1] H. S. Patel and R. G. Hoft, “Generalized harmonic elimination and voltage control in thyristor converters: Part I—Harmonic elimination,” IEEE Trans. Ind. Appl., vol. IA-9, no. 3, pp. 310–317, May 1973. [2] H. S. Patel and R. G. Hoft, “Generalized harmonic elimination and voltage control in thyristor converters: Part II—Voltage control technique,” IEEE Trans. Ind. Appl., vol. IA-10, no. 5, pp. 666–673, Sep. 1974. [3] J. Napoles, A. Watson, J. Padilla, J. Leon, L. Franquelo, W. Patrick, and M. Aguirre, “Selective harmonic mitigation technique for cascaded Hbridge converters with non-equal DC link voltages,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1963–1971, May 2013. [4] J. Napoles, J. I. Leon, R. Portillo, L. G. Franquelo, and M. A. Aguirre, “Selective harmonic mitigation technique for high-power converters,” IEEE Trans. Ind. Electron., vol. 57, no. 7, pp. 2315–2323, Jul. 2010. [5] L. G. Franquelo, J. Napoles, R. Portillo, J. I. Leon, and M. A. Aguirre, “A flexible selective harmonic mitigation technique to meet grid codes in three-level PWM converters,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 3022–3029, Dec. 2007. [6] K. Gopakumar, N. A. Azeez, J. Mathew, A. Dey, and M. Kazmierkowski, “A medium voltage inverter fed IM drive using multilevel 12-sided polygonal vectors, with nearly constant switching frequency current hysteresis controller,” IEEE Trans. Ind. Electron., vol. 61, no. 4, pp. 1700–1709, Apr. 2014. [7] B. Sanzhong and S. M. Lukic, “New method to achieve AC harmonic elimination and energy storage integration for 12-pulse diode rectifiers,” IEEE Trans. Ind. Electron., vol. 60, no. 7, pp. 2547–2554, Jul. 2013. [8] F. Filho, H. Z. Maia, T. H. A. Mateus, B. Ozpineci, L. M. Tolbert, and J. O. P. Pinto, “Adaptive selective harmonic minimization based on ANNs for cascade multilevel inverters with varying DC sources,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1955–1962, May 2013. [9] S. R. Pulikanti, G. Konstantinou, and V. G. Agelidis, “Hybrid seven-level cascaded active neutral-point-clamped-based multilevel converter under SHE-PWM,” IEEE Trans. Ind. Electron., vol. 60, no. 11, pp. 4794–4804, Nov. 2013. [10] J. I. Guzman, P. E. Melin, J. R. Espinoza, L. A. Moran, C. R. Baier, J. A. Munoz, and G. A. Guinez, “Digital implementation of selective harmonic elimination techniques in modular current source rectifiers,” IEEE Trans. Ind. Informat., vol. 9, no. 2, pp. 1167–1177, May 2013. [11] J.-S. Lai and F. Z. Peng, “Multilevel converters—A new breed of power converters,” IEEE Trans. Ind. Appl., vol. 32, no. 3, pp. 509–517, May/Jun. 1996. [12] C. Buccella, C. Cecati, and M. G. Cimoroni, “Investigation about numerical methods for selective harmonics elimination in cascaded multilevel inverters,” in Proc. Int. Conf. ESARS Propulsion, Bologna, Italy, Oct. 2012, pp. 1–6. 5818 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 11, NOVEMBER 2014 [13] C. Buccella, C. Cecati, and M. G. Cimoroni, “Harmonics elimination in 5-level converters operating at very low switching frequency,” in Proc. IEEE ICIT, Cape Town, South Africa, Feb. 24–27, 2013, pp. 1946–1951. [14] F. Z. Peng, J.-S. Lai, J. W. McKeever, and J. VanCoevering, “A multilevel voltage-source inverter with separate DC sources for static VAr generation,” IEEE Trans. Ind. Appl., vol. 32, no. 5, pp. 1130–1138, Sep./Oct. 1996. [15] J. Vassallo, J. C. Clare, and P. W. Wheeler, “A power-equalized harmonicelimination scheme for utility-connected cascaded H-bridge multilevel converters,” in Proc. IEEE 29th IECON/IECON, Nov. 2–6, 2003, vol. 2, pp. 1185–1190. [16] H. L. Liu, G. H. Cho, and S. S. Park, “Optimal PWM design for high power three-level inverter through comparative studies,” IEEE. Trans. Power Electron., vol. 10, no. 1, pp. 38–47, Jan. 1995. [17] J. Kumar, B. Das, and P. Agarwal, “Selective harmonic elimination technique for a multilevel inverter,” in Proc. 15th NPSC, Bombay, India, Dec. 2008, pp. 608–613, IIT. [18] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, “Multilevel converters for large electric drives,” IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 36–44, Jan./Feb. 1999. [19] J. Sun and I. Grotstollen, “Pulsewidth modulation based on real-time solution of algebraic harmonic elimination equations,” in Proc. 20th IEEE IECON/IECON, Sep. 5–9, 1994, vol. 1, pp. 79–84. [20] L. Li, D. Czarkowski, Y. Liu, and P. Pillay, “Multilevel selective harmonic elimination PWM technique in series-connected voltage inverters,” IEEE Trans. Ind. Appl., vol. 36, no. 1, pp. 160–170, Jan./Feb. 2000. [21] T. Tang, J. Han, and X. Tan, “Selective harmonic elimination for a cascade multilevel inverter,” in Proc. IEEE ISIE, Jul. 2006, vol. 2, pp. 977–981. [22] W. Fei, X. Du, and B. Wu, “A generalized half-wave symmetry SHEPWM formulation for multilevel voltage inverters,” IEEE Trans. Ind. Electron., vol. 57, no. 9, pp. 3030–3038, Sep. 2010. [23] T. J. Liang, R. M. O’Connell, and R. G. Hoft, “Inverter harmonic reduction using Walsh function harmonic elimination method,” IEEE Trans. Power Electron., vol. 12, no. 6, pp. 971–982, Nov. 1997. [24] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and Z. Du, “Control of a multilevel converter using resultant theory,” IEEE Trans. Control Syst. Technol., vol. 11, no. 3, pp. 345–353, May 2003. [25] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, and Z. Du, “A unified approach to solving the harmonic elimination equations in multilevel converters,” IEEE Trans. Power Electron., vol. 19, no. 2, pp. 478–490, Mar. 2004. [26] B. Ozpineci, L. M. Tolbert, and J. N. Chiasson, “Harmonic optimization of multilevel converters using genetic algorithms,” IEEE Power Electron. Lett., vol. 3, no. 3, pp. 92–95, Sep. 2005. [27] R. Salehi, N. Farokhnia, M. Abedi, and S. H. Fathi, “Elimination of low order harmonics in multilevel inverter using genetic algorithm,” J. Power Electron., vol. 11, no. 2, pp. 132–139, Mar. 2011. [28] M. S. A. Dahidah and V. G. Agelidis, “Selective harmonic elimination PWM control for cascaded multilevel voltage source converters: A generalized formula,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1620– 1630, Jul. 2008. [29] A. Kavousi, B. Vahidi, R. Salehi, M. Bakhshizadeh, N. Farokhnia, and S. S. Fathi, “Application of the bee algorithm for selective harmonic elimination strategy in multilevel inverters,” IEEE Trans. Power Electron., vol. 27, no. 4, pp. 1689–1696, Apr. 2012. [30] M. T. Hagh, H. Taghizadeh, and K. Razi, “Harmonic minimization in multilevel inverters using modified species-based particle swarm optimization,” IEEE Trans. Power Electron., vol. 24, no. 10, pp. 2259–2267, Oct. 2009. [31] A. Kaviani, S. H. Fathi, N. Farokhnia, and A. Ardakani, “PSO, an effective tool for harmonics elimination and optimization in multilevel inverters,” in Proc. 4th IEEE Conf. Ind. Electron. Appl., May 25–27, 2009, pp. 2902–2907. [32] K. Shen, D. Zhao, J. Mei, L. M. Tolbert, J. Wang, M. Ban, Y. Ji, and X. Cai, “Elimination of harmonics in a modular multilevel converter using particle swarm optimization-based staircase modulation strategy,“ IEEE Trans. Ind. Electron., vol. 61, no. 10, pp. 5311–5322, Oct. 2014. [33] R. Salehi, B. Vahidi, N. Farokhnia, and M. Abedi, “Harmonic elimination and optimization of stepped voltage of multilevel inverter by bacterial foraging algorithm,” J. Elect. Eng. Technol., vol. 5, no. 4, pp. 545–551, Dec. 2010. [34] K. Sundareswaran, K. Jayant, and T. N. Shanavas, “Inverter harmonic elimination through a colony of continuously exploring ants,” IEEE Trans. Ind. Electron., vol. 54, no. 5, pp. 2558–2565, Oct. 2007. [35] T. Kato, “Sequential homotopy-based computation of multiple solutions for selected harmonic elimination in PWM inverters,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 46, no. 5, pp. 586–593, May 1999. [36] J. Sun, S. Beineke, and H. Grotstollen, “Optimal PWM based on realtime solution of harmonic elimination equations,” IEEE Trans. Power Electron., vol. 11, no. 4, pp. 612–621, Jul. 1996. [37] Y. X. Xie, L. Zhou, and H. Peng, “Homotopy algorithm research of the inverter harmonic elimination PWM model,” Proc. Chin. Soc. Elect. Eng., vol. 20, no. 10, pp. 23–26, 2000. [38] V. G. Agelidis, A. Balouktsis, and I. Balouktsis, “On applying a minimization technique to the harmonic elimination PWM control: The bipolar waveform,” IEEE Power Electron. Lett., vol. 2, no. 2, pp. 41–44, Jun. 2004. [39] V. G. Agelidis, A. Balouktsis, and C. Cosar, “Multiple sets of solutions for harmonic elimination PWM bipolar waveforms: Analysis and experimental verification,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 415–421, Mar. 2006. [40] M. Abramowitz and I. A. Stegun, Handbook of Mathematical Functions. Washington, DC, USA: National Bureau of Standards, 1964, ser. Applied Mathematics Series 55. [41] I. G. Mac Donald, Symmetric Functions and Hall Polynomials. Oxford, U.K.: Clarendon Press, 1995. [42] C. Buccella, C. Cecati, and H. Latafat, “Digital control of power converters—A survey,” IEEE Trans. Ind. Informat., vol. 8, no. 3, pp. 437– 447, Aug. 2012. [43] C. Cecati, “Microprocessors for power electronics and electrical drives applications,” IEEE Ind. Electron. Soc. Newslett., vol. 46, no. 3, pp. 5–9, Sep. 1999. [44] J. Holtz and N. Oikonomou, “Synchronous optimal pulsewidth modulation and stator flux trajectory control for medium-voltage drives,” IEEE Trans Ind. Appl., vol. 43, no. 2, pp. 600–608, Mar./Apr. 2007. [45] M. F. Escalante, J. C. Vannier, and A. Arzande, “Flying capacitor multilevel inverters and DTC motor drive applications,” IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 809–815, Aug. 2002. [46] Matlab 7.13 (R2011b) Software Package. [Online]. Available: http:// www.Mathworks.com [47] [Online]. Available: http://www.mcselec.com/? option=com_content&task=view&id=14&Itemid=41 [48] [Online]. Available: www.xilinx.com/support/download/ Concettina Buccella (M’92–SM’03) received the Dr. Eng. degree in electrical engineering from the University of L’Aquila, L’Aquila, Italy, and the Ph.D. degree in electrical engineering from the University of Rome “La Sapienza,” Rome, Italy, in 1988. From 1988 to 1989, she was with Italtel S.p.A., L’Aquila, Italy. Then, she joined the University of L’Aquila, where she has been an Associate Professor since 2001. She is the C.E.O. of DigiPower Ltd., L’Aquila, Italy. Her research interests include power converters, power systems, smart grids, electromagnetic compatibility, electrostatic processes, and ultrawideband signal interferences. Dr. Buccella was a corecipient of the 2012 and 2013 IEEE T RANSACTIONS ON I NDUSTRIAL I NFORMATICS Best Paper Award. Carlo Cecati (M’90–SM’03–F’06) received the Dr. Ing. degree in electrotechnical engineering from the University of L’Aquila, L’Aquila, Italy, in 1983. Since 1983, he has been with the University of L’Aquila, where he is currently a Professor of Industrial Electronics and Drives. He is also a Guest Professor with the Harbin Institute of Technology, Harbin, China. In 2007, he was a Co-founder of DigiPower Ltd., L’Aquila, Italy. His research and technical interests cover several aspects of power electronics, electrical drives, digital control, distributed generation, and smart grids. Dr. Cecati is the current Editor-in-Chief of the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS. BUCCELLA et al.: ANALYTICAL METHOD FOR PATTERN GENERATION IN H-BRIDGE INVERTER USING SHE Maria Gabriella Cimoroni received the M.S. degree in mathematics (summa cum laude) from the University of L’Aquila, L’Aquila, Italy, in 1989. After graduation she attended the postgraduate InterUniversity School of Perugia, Perugia, Italy, and the CNR Computational Mathematics School at Naples, Naples, Italy. Since 1997, she has been a Researcher in numerical analysis with the University of L’Aquila. Her research interests deal with analytical and numerical methods for control and management of power converters, function approximation techniques, and modulation algorithms for multilevel converters. 5819 Kaveh Razi was born in Tabriz, Iran. He received the B.Sc. degree in electronic engineering from Islamic Azad University, Tabriz Branch, Tabriz, Iran, and the M.Sc. degree in power electronics from the University of Tabriz, Tabriz, Iran, in 2005 and 2008, respectively. He is currently working toward the Ph.D. degree at the University of L’Aquila, L’Aquila, Italy. His research interests include the development of power electronics converters, renewable photovoltaic (PV) systems, artificial intelligence applications, and digital control using microcontrollers, digital signal processors (DSPs), and field-programmable gate arrays (FPGAs).