IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 2025 230-GHz Self-Aligned SiGeC HBT for Optical and Millimeter-Wave Applications Pascal Chevalier, Cyril Fellous, Laurent Rubaldo, Franck Pourchon, Sébastien Pruvost, Rudy Beerkens, Fabienne Saguin, Nicolas Zerounian, Benoît Barbalat, Sylvie Lepilliet, Didier Dutartre, Didier Céli, Isabelle Telliez, Daniel Gloria, Frédéric Aniel, Member, IEEE, François Danneville, Member, IEEE, and Alain Chantre, Senior Member, IEEE Abstract—This paper describes a 230-GHz self-aligned SiGeC heterojunction bipolar transistor developed for a 90-nm BiCMOS technology. The technical choices such as the selective epitaxial growth of the base and the use of an arsenic-doped monocrystalline emitter are presented and discussed with respect to BiCMOS performance objectives and integration constraints. DC and high-frequency device performances at room and cryogenic temperatures are given. HICUM model agreement with the measurements is also discussed. Finally, building blocks with state-of-the-art performances for a CMOS compatible technology are presented: A ring oscillator with a minimum stage delay of 4.4 ps and a 40-GHz low-noise amplifier with a noise figure of 3.9 dB and an associated gain of 9.2 dB were fabricated. Index Terms—BiCMOS integrated circuits, heterojunction bipolar transistors, millimeter-wave circuits, optical communication. I. INTRODUCTION S iGeC heterojunction bipolar transistors (HBTs) have demonstrated cut-off frequencies, and , higher than 200 GHz [1]–[3]. These performances are very interesting when they are offered in a BiCMOS environment with an advanced CMOS node allowing the integration of complex digital blocks. BiCMOS technologies already dominate existing wireline communications ( 10 Gb/s) and are going to conquer next optical generations (40 and 80 Gb/s). Wireless applications below 10 GHz are today covered by CMOS and BiCMOS technologies but millimeter-wave circuits were still within the sphere of III-V technologies. Henceforth, BiCMOS technologies with cut-off frequencies above 200 GHz target millimeter-wave applications such as 77-GHz automotive radars [4]. STMicroelectronics’ roadmap includes a 230-GHz Manuscript received November 26, 2004; revised March 21, 2005. A preliminary version of this paper was presented at the IEEE Bipolar/BiCMOS Circuit and Technology Meeting, September 2004, Montreal, Canada. P. Chevalier, C. Fellous, L. Rubaldo, F. Pourchon, F. Saguin, D. Dutartre, D. Gloria, D. Céli, I. Telliez, and A. Chantre are with STMicroelectronics, F-38926 Crolles, France (e-mail: pascal.chevalier@st.com). S. Pruvost is with STMicroelectronics, F-38926 Crolles, France, and also with IEMN-DHS, Villeneuve d’Ascq, France. R. Beerkens is with STMicroelectronics, Ottawa, ON K2H 8R6, Canada. N. Zerounian and F. Aniel are with IEF, Université Paris-Sud 11, F-91405 Orsay, France. B. Barbalat is with STMicroelectronics, F-38926 Crolles, France, and also with IEF, Université Paris-Sud 11, F-91405 Orsay, France. S. Lepilliet and F. Danneville are with IEMN-DHS, UMR CNRS 8520, USTL, 59652 Villeneuve d’Ascq, France. Digital Object Identifier 10.1109/JSSC.2005.852846 SiGeC BiCMOS technology based on a 90-nm CMOS platform to address these wireless and wireline markets. In order to comply with this objective, we have investigated a fully self-aligned (FSA) HBT architecture, in contrast with previous in-house technologies. In this paper, we first motivate the main technological choices that have been made to reach the objective: the selective epitaxial growth (SEG) of the base and the arsenic in situ doped monoemitter. Second, we describe the FSA-SEG bipolar technology with some highlights on key difficulties that have been solved. Then, static and dynamic characteristics at room and cryogenic temperatures of a HBT are shown and comparisons with 220/230-GHz HICUM model [21] are discussed. Finally, we present ring oscillator and 40-GHz low-noise amplifier circuits results and conclude on this technology. This paper is an extended version of [5]. II. MOTIVATIONS FOR AN FSA-SEG SiGeC HBT WITH AN ARSENIC DOPED MONOEMITTER A. Bipolar Architecture High-speed and RF SiGeC HBTs integrated in STMicroelectronics BiCMOS technologies have always been based on a quasi-self aligned (QSA) emitter-base architecture together with a nonselective epitaxial growth (NSEG) of the base (see Table I). The 0.35- m BiCMOS technology [6] uses a single-polysilicon architecture while a more efficient double-polysilicon QSA architecture was developed for 0.25- m [7] and 0.13- m [8] generations. and higher than 150 GHz have been Remarkably, demonstrated using this architecture [8]. We believe that the performance of this QSA architecture can be extended to over 200 GHz , but would request aggressive overlay design rules because of the excess of parasitics, to reach 230 GHz namely the extrinsic base resistance and the collector-base capacitance, introduced by the lack of self-alignment. This observation is confirmed by the results presented in [9]. Consequently, we made the choice to investigate an FSA architecture for 90-nm BiCMOS generation. Two solutions exist to get the self-alignment: using a selective epitaxial growth of the base into a double-poly architecture or a nonselective epitaxial growth of the base together with an emitter replacement technique. Schematic cross sections of these architectures, with identical design rules, are given in Fig. 1: the FSA-NSEG structure [Fig. 1(a)] is based on 0018-9200/$20.00 © 2005 IEEE 2026 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 TABLE I STMICROELECTRONICS HIGH-SPEED BiCMOS TECHNOLOGIES [1] while the FSA-SEG structure [Fig. 1(b)] corresponds to the technology presented here. It is important to mention that dimensions in Fig. 1 are identical for the two structures to highlight the main differences, but different design rules could be needed for their respective optimization. We have studied the pros and cons of both solutions. FSA-NSEG structures using emitter replacement techniques offer the advantage of the nonselective epitaxial growth of the SiGeC base. It is a proven deposition process (in production at STMicroelectronics) for which carbon’s ability to efficiently block boron diffusion has been demonstrated [10]. The emitter construction details are rarely described in the literature [11], [12]. The techniques that are known or surmised to be used are chemical–mechanical polishing (CMP) [13] or counter mask (image reversal) lithography [14]. They offer the advantage of an emitter width defined by a CMOS gate-like process, allowing narrow emitters. The associated drawbacks are the deposition of the final emitter after etching of the sacrificial emitter, which may be difficult depending on the aspect ratio, and the related emitter resistance increase. A way to avoid these issues is to widen the sacrificial emitter and to insert inside spacers, but the advantage of the emitter width being defined by direct patterning then vanishes. In addition, these architectures become competitive at the expense of the selective epitaxy of (raised) extrinsic base regions (p+) in order to avoid extrinsic base implantation damage [11]. This module is interesting since it provides a monocrystalline intrinsic–extrinsic base link, but the epitaxial process must be optimized in order to avoid any influence of the thermal budget on the intrinsic base (boron diffusion issue). Furthermore, processes based on CMP or counter mask lithography techniques are not easy to implement and/or to integrate in a BiCMOS flow. The FSA-SEG structure [2], [3] can either be viewed as a simple or a complex evolution of the standard double-polysilicon bipolar transistor architecture, depending whether we consider it as a natural evolution of a proven architecture (most of the process steps are unchanged) or that it requires Fig. 1. Schematic cross sections of self-aligned HBT’s using (a) nonselective and (b) selective epitaxy of the base. a sensitive process step (the selective epitaxy of thin and complicated films). First, while the architectures discussed previously are self-aligned (SA), the SEG structure is super self-aligned (SSA). The selective collector implant (SIC) is indeed performed through the emitter window and is consequently aligned to the emitter without any additional mask. The effective active area is aligned to the emitter as well, since it is defined by the isotropic etching of a pedestal oxide exposed by the emitter window opening. Besides, this sacrificial oxide for the base layer cavity offers the advantage of good isolation CHEVALIER et al.: 230-GHz SELF-ALIGNED SiGeC HBT FOR OPTICAL AND MILLIMETER-WAVE APPLICATIONS between the extrinsic base and the collector area. It provides a narrow effective active area allowing a low collector-base capacitance. In contrast, the transition from monosilicon to polysilicon at shallow trench edges limits the reduction of the active area of FSA-NSEG devices. Second, narrow emitters can be obtained thanks to an inside spacer module without any m demanding lithography: we have indeed fabricated emitters using 248-nm deep-UV lithography. This structure also requests fewer lithography steps than NSEG architectures. The only drawback of using the FSA-SEG structure is, of course, the selective epitaxial growth process itself, since it rises many questions about micro- (layout dependent variations) and macro- (variations within a wafer) loading effects (this last one is also present with NSEG) and more recently about carbon efficiency to block boron diffusion [15]. Consequently, comparing the advantages and drawbacks of the different solutions, including the BiCMOS integration capabilities, we decided to investigate the FSA-SEG structure. We will show hereafter that the difficulties of the selective epitaxial growth have been successfully addressed. B. Arsenic In Situ Doped Monoemitter The best performances of SiGe HBT to date have been reported for devices featuring a phosphorous in situ doped emitter [1]–[11]. Indeed, the two main advantages of phosphorous emitters are the lower emitter resistance and the reduced thermal budget for dopant drive-in. However, this last point can become a constraint in a BiCMOS context since the final CMOS spike activation anneal can no longer be applied at the end of the front-end processing. Indeed, to avoid CMOS re-engineering and thus to reduce process developments, the CMOS activation anneal is usually kept in the derived BiCMOS technology. This annealing (at around 1100 C) leads to an excessive diffusion of the phosphorous. Different ways to integrate the CMOS activation anneal into the fabrication of a phosphorous doped emitter bipolar exist, but none of them are easy to implement. Thus, we decided to keep using an arsenic in situ doped polyemitter. It is, in fact, a monoemitter, since it is epitaxially aligned onto the base [16], allowing a reduced emitter resistance. III. PROCESS DESCRIPTION The FSA-SEG bipolar anticipation action for 90-nm BiCMOS uses 0.13- m BiCMOS reticles and core process [8]. The fabrication starts with the formation of a n+ buried layer on a p-substrate, followed by thin collector epitaxy and deep trench isolation. After definition of the active area by shallow trench, the collector sinker is implanted. Next, a pedestal oxide/polybase/oxide/nitride stack is deposited and patterned. A 0.3- m emitter window is patterned and etched in this stack, stopping on the pedestal oxide layer. An SIC is performed and nitride sidewalls are formed to protect the polybase from the base epitaxy. The pedestal oxide is then wet etched to open the base cavity. The selective growth of the SiGeC base is done in a single wafer RTCVD reactor. An H bake is applied prior to the 2027 Fig. 2. SEM picture of the SiGeC FSA-SEG bipolar. deposition. CMOS devices in this BiCMOS technology will not be affected by this bake since it is inserted prior to the formation of CMOS source/drain regions [8]. Next, L-shaped inside spacers are fabricated to get a final emitter width 0.17 m. Arsenic in situ doped polysilicon is deposited to form the emitter. After polyemitter patterning, spike activation anneal at 1100 C, cobalt silicidation and contact formation complete the fabrication sequence. The back-end of line (BEOL) features six copper metal levels and an aluminum capping layer. An SEM cross section of the HBT is shown in Fig. 2. SEG process is often avoided due to micro- or macro-loading effects, even though they can be efficiently minimized. Indeed, our electrical results discussed below do not exhibit any process uniformity issues. The main difficulty with selective epitaxy of SiGeC is the higher growth temperature (especially with a nitride mask) compared to nonselective epitaxy, which is detrimental to the carbon incorporation on substitutional sites. However, we have shown that the carbon profile can be optimized to efficiently block the boron diffusion [17]. The 20-nm-thick base features a germanium profile graded from collector (30%) to cm surrounded emitter (20%) with a boron spike of by carbon. The high Ge content at emitter-base junction has the double objective of reducing the emitter transit time and limiting the boron diffusion toward the emitter. of an FSA-SEG The low collector-base capacitance transistor relies both on small collector-base area and on self-alignment of the SIC on the emitter window. To further , we have replaced phosphorous by arsenic as reduce the SIC dopant, which is possible in the FSA-SEG process because the SIC implant is before the base deposition (arsenic has a smaller implant range at a given energy than does phosphorous). The lower diffusion of arsenic atoms allows better control of the vertical profile of the SIC but also reduces lateral . The diffusivity of phosphorous is diffusion, benefiting such that it is difficult to get a precise control of the doping profile, especially for the doping levels used ( 10 cm ). It is therefore much easier to control different collector doping levels between base and buried layer with arsenic than with phosphorous. The arsenic SIC allows a 10% reduction of for the same base-collector breakdown voltage and , leading (compared to phosphorous). to a 5% increase of 2028 Fig. 3. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 Gummel characteristics of a 0:17 0:17 2 0:5 m HBT array. Fig. 4. 0J 2 3:6 m HBT and of a 1000 2 characteristics for different transistor lengths (same die). IV. SiGeC BIPOLAR TRANSISTORS PERFORMANCES A. DC Characteristics Fig. 3 shows Gummel plots of both a single transistor with m and an array of a thousand an emitter area of transistors with a unity emitter area of m . Ideal cur. The rent characteristics are obtained down to a low (collector current density) characteristic is remarkably constant whatever the emitter length from 0.5 to 15 m (Fig. 4) and width [18], which confirms the absence of micro-loading efis about 1700 at fects. The maximum current gain 0.5 mA m 0.6 V . The Early voltage extracted from common emitter forcedoutput characteristics (Fig. 5) at medium collector currents (where there is no self-heating) is close to 180 V. This is made possible by a pinched base resistance value below 2 k sq. The , derived from collector-emitter breakdown voltage base current reversal measurements, is 1.6 V at medium injecV . Open emitter collector-base breakdown tion voltage is measured around 5.6 V. B. HF Characteristics and curves at 300 K and 55 K Fig. 6 shows and at V for a m CBEBC bipolar transistor. Room temperature characteristics, extracted from S-paand of rameter measurements up to 110 GHz, exhibit 220 and 230 GHz, respectively. This performance is reached at a Fig. 5. I –V Fig. 6. f and 55 K. and f characteristics of a 0:17 versus J 2 3:6  m curves of a 0:17 transistor. 2 3:6  m HBT at 300 K collector current density of about 12 mA m . We have shown is constant at 220 GHz while decreases from in [5] that 240 GHz to 220 GHz for emitter lengths varying from 1.6 m at V for a wider range to 5.6 m. (Fig. 10 shows of emitter lengths.) increase to 350 GHz at 55 K (Fig. 6). The Both and simultaneous increase of and demonstrates on one hand the excellent ability of these HBTs to operate at cryogenic temperatures and on the other hand the low parasitic components of this architecture. This is, to our knowledge, the best reported performance of a SiGeC HBT at cryogenic temperature [19]. extrapolated at V are, Forward transit times respectively, 0.62 ps at 300 K and 0.40 ps at 55 K (Fig. 7). The extraction procedure presented in [20] shows that this reduction is spread over both transit and charging times. is less straightforward than The determination of and requires some discussion. In our work, we employ various . The preferred one, used to get the methods to extract curves of Fig. 6, is the extrapolation at 20 dB/decade toward dB. is then simply 0 of the Mason gain when expressed by the multiplication by 10 of the frequency corredB. sponding to Another method is the extrapolation of in the frequency range 8–18 GHz with the natural slope of in this range. values of 239 and 238 GHz are respectively obtained from Fig. 8 with these two methods, which shows that the decrease of with the frequency is very close to 20 dB/decade. Values of at CHEVALIER et al.: 230-GHz SELF-ALIGNED SiGeC HBT FOR OPTICAL AND MILLIMETER-WAVE APPLICATIONS Fig. 7.  versus 1=I curves of a 0:17 55 K for different V . 2 3:6 m 2029 transistor at 300 K and Fig. 10. Measurements (symbols) versus HICUM simulations (solid lines) of = 0 V for a wide range of emitter lengths. the f versus I at V 2 Fig. 8. U –f curve of a 0:17 3:6 m 240 GHz f = 0:92 V (T = 300 K). 0:5 V and V transistor at V = Fig. 11. I –V measurements (symbols) versus simulations with activated (solid lines) or de-activated thermal sub-circuit (dotted lines) of a 0:17 14:8 m transistor for different V . 2 Fig. 9. f mapping [GHz] with 3:6 m transistor at V f and = 0:5 V and V f statistics [GHz] of a 0:17 = 0:92 V (T = 300 K). 2 different frequencies provide a good mean to check the validity of the extraction. They are also given in Fig. 8. wafer map presented in Fig. 9 shows a standard deThe viation of 2.5% (4.8% for ), demonstrating the absence of significant macro-loading effects during SiGeC base epitaxy. V. DEVICE MODELING To give designers early access to the technology, a model library has been developed. This library uses the advanced HICUM [21] model whose accuracy allows designers to more fully utilize the device performance. This model overcomes the main issues of the classical SPICE Gummel–Poon (SGP) model and is especially dedicated to high current densities and high-frequency modeling. It is a physics-based compact model that features all relevant effects occurring in advanced bipolar transistors including temperature effects and self-heating. The available library is scalable, meaning designers are allowed to use bipolar transistors with different configurations (single emitter with one or two base contacts, one or two collector contacts, or multi-emitter structures) in a wide range of emitter lengths. For design optimization, this approach is more suitable than the discrete approach. Fig. 10 shows – characteristics for transistors with different emitter lengths. Final emitter dimensions are indicated as labels. The accuracy of the model library from low to high infall-off, is demonstrated. jection, even for The self-heating description is critical for model accuracy because these transistors drive high current densities through narrow emitter widths and are isolated with deep trenches. This phenomenon is accounted for in HICUM via a thermal sub-cirand a capacitance in parcuit with a resistance allel. The and model is scalable as well. Fig. 11 aims to show in which DC bias conditions the thermal m device, sub-circuit is the most needed. For a 2030 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 Fig. 13. CML stage delay versus tail current. Fig. 12. f –I measurements (symbols) versus simulation with activated (solid lines) or de-activated thermal sub-circuit (dotted lines) of a 0:17 3:6 m transistor for different V . Simulator device temperature is plotted on the secondary Y axis. 2 the collector current is plotted sweeping up to large values (beyond V) for different values. From this and high (where figure, it is clear that under high power dissipated in the device is high), modeling without selfheating leads to inaccurate simulated value (up to 100% error for V). For lower than 0.80 V, the device internal temperature is the ambient temperature, thus the thermal sub-circuit is not required. m device, the – characteristics For a for different , with and without self-heating included in simulation, are plotted in Fig. 12. There is no major difference V value between both simulations. for low To the contrary for the highest collector-emitter bias value V , the HICUM library without the thermal . Actisub-circuit activated overestimates the maximum vating the sub-circuit, the simulations match the measurements very well because the thermal sub-circuit accounts for degradation due to the internal device temperature rise. The internal device temperature computed by the simulator (accessible thanks to the HICUM model thermal node) is plotted on the secondary Y axis in Fig. 12. This temperature does not represent an exact junction temperature, but should be an effective temperature that describes the global device heating. This figure confirms that increasing the collector bias raises the power dissipated in the device, and gives an increase of the internal device temperature up to 70 C at peak . VI. CIRCUIT PERFORMANCE A. Ring Oscillators The family of ring oscillators designed for the 0.13- m BiCMOS technology [8] was fabricated in this bipolar process. They consist of 23 stages of current-mode logic (CML) inverters with unity fan-out, and emitter lengths ranging from 0.5 to 2.4 m. The internal voltage swing is 200 mV. The dependence of the stage delay time on the tail current is indicated in Fig. 13. A minimum stage delay of 4.4 ps was observed for the 2.4- m emitter lengths, despite having nonoptimal load resistance. Fig. 14. Noise figure measured on 50- ports (NF ) and HICUM simulations for NF and minimum noise figure (NF ) at V = 1:5 V (I = 5:5 mA). B. Low-Noise Amplifier (LNA) Low-noise amplifiers operating at 40 GHz have also been designed for the 0.13- m BiCMOS technology [8]. They have been fabricated in this bipolar process in order to evaluate the capabilities of the 90-nm BiCMOS technology for millimeterwave applications. Small-signal and noise characteristics were retro-simulated using the HICUM model. The LNA presented here features a simple one-stage topology. The transistor selected for this design is a symmetrical device featuring three emitter fingers of 3 m length each m . It exhibits and of, respectively, 205 GHz and more than 240 GHz. The Maximum Stable Gain of the transistor is about 16 dB at 40 GHz. The de-embedded transistor (i.e., transistor without pads and access lines required for measurement) provides a simulated minimum noise figure of 1.7 dB (Fig. 14) and an associated measured gain of 12 dB at 40 GHz. Fig. 14 shows that HICUM model also gives an excellent prediction of the noise figure. BiCMOS technologies feature nonoptimized metal interconnects for millimeter-wave frequencies compared to GaAs, InP, or Si bipolar only technologies with dedicated BEOL. The design approach is then based on a compact layout using optimized passive structures, here micro-strip propagation waveguides. Similar approach was applied in [22] with SOI CMOS technology. A representation of the one-stage amplifier is presented in Fig. 15. Measurements and simulations of the amplifier are shown in Fig. 16. The full one-stage LNA measurements are CHEVALIER et al.: 230-GHz SELF-ALIGNED SiGeC HBT FOR OPTICAL AND MILLIMETER-WAVE APPLICATIONS Fig. 15. 0:42 Die representation of the single-stage low-noise amplifier (0:47 ). < 0:2 mm 2 2031 budget. The bipolar device has been developed for 90-nm BiCMOS technology, even though it could be integrated in another CMOS node (0.13 m or 65 nm) with the same performance, depending on customer needs. Results obtained on ring oscillators and a 40-GHz LNA show indeed that a 230-GHz BiCMOS technology will be able to cover both optical and millimeter-wave applications. These state-of-the-art results for a CMOS-compatible technology can be further improved since these blocks were not initially designed for this technology. The CMOS compatibility is indeed detrimental both for the bipolar transistor (higher thermal budget) and the passive devices (BEOL not optimized for millimeter-wave frequencies) that have a major impact on LNA performance. The LNA results also validate the modeling accuracy, a modeling work that clearly demonstrates the need for a thermal sub-circuit to take into account self-heating effects that occur in bipolar devices with this performance level. ACKNOWLEDGMENT The authors wish to thank the many members of the 200 mm Si plant in STMicroelectronics Crolles involved in the various aspects of this work. The managerial support of M. Roche, A. Fleury, and B. Sautreuil is also gratefully acknowledged. REFERENCES Fig. 16. S-parameters and noise figure of the single stage low-noise amplifier: measurements (symbols) versus HiCUM simulations (lines) at V = 1:5 V (I = 5:1 mA). reported for the circuit’s optimum noise biasing. The tradeoff between input return loss and optimum noise matching is difficult to achieve in a one-stage design. This explains why optimum input matching is not obtained at 40 GHz for the optimum noise matching. Finally, the one-stage SiGeC HBT LNA exhibits a total frequency range from 24 to 39 GHz with input return loss of 10 dB at 40 GHz and a 3.9 dB associated noise figure (less than 5 dB from 30 to 40 GHz). Output return loss has been previously established to be less than 10 dB without RF access pad, and confirmed by measurement. The power gain is higher than 9.2 dB at 40 GHz with less than 8 mW power consumption. Furthermore, these measurements are in excellent correlation with simulation using HICUM model. VII. CONCLUSION We have presented world-class performances of a CMOS-compatible 230-GHz SiGeC HBT technology. The main features of the device include a fully self-aligned architecture, a SiGeC base grown using selective epitaxy, and an arsenic doped monoemitter. These technical choices have been made to facilitate the BiCMOS integration since these performances are reached for an HBT sustaining a high thermal [1] B. Jagannathan, M. Khater, F. Pagette, J.-S. Rieh, D. Angell, H. Chen, J. Florkey, F. Golan, D. R. Greenberg, R. Groves, S. J. Jeng, J. Johnson, E. Mengistu, K. T. Schonenberg, C. M. Schnabel, P. Smith, A. Stricker, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna, “Self-aligned SiGe and 207 GHz f in a manuNPN transistors with 285 GHz f facturable technology,” IEEE Electron Device Lett., vol. 23, no. 5, pp. 258–260, May 2002. [2] T. Hashimoto, Y. Nonaka, T. Tominari, H. Fujiwara, K. Tokunaga, M. Arai, S. Wada, T. Udo, M. Seto, M. Miura, H. Shimamoto, K. Washio, and H. Tomioka, “Direction to improve SiGe BiCMOS technology featuring 200-GHz SiGe HBT and 80-nm gate CMOS,” in IEDM Tech. Dig., 2003, pp. 129–132. [3] T. F. Meister, H. Schäfer, K. Aufinger, R. Stengl, S. Boguth, R. Schreiter, M. Rest, H. Knapp, M. Wurzer, A. Mitchell, T. Böttner, and J. Böck, “SiGe bipolar technology with 3.9 ps gate delay,” in Proc. BCTM, 2003, pp. 103–106. [4] P. Wennekers and R. Reuter, “SiGe technology requirements for millimeter-wave applications,” in Proc. BCTM, 2004, pp. 79–83. [5] P. Chevalier, C. Fellous, L. Rubaldo, D. Dutartre, M. Laurens, T. Jagueneau, F. Leverd, S. Bord, C. Richard, D. Lenoble, J. Bonnouvrier, M. Marty, A. Perrotin, D. Gloria, F. Saguin, B. Barbalat, R. Beerkens, N. Zerounian, F. Aniel, and A. Chantre, “230 GHz self-aligned SiGeC HBT for 90-nm BiCMOS technology,” in Proc. BCTM, 2004, pp. 225–228. [6] A. Monroy, M. Laurens, M. Marty, D. Dutartre, D. Gloria, J. L. Carbonero, A. Perrotin, M. Roche, and A. Chantre, “A high performance 0.35 m SiGe BiCMOS technology for wireless applications,” in Proc. BCTM, 1999, pp. 121–124. [7] H. Baudry, B. Martinet, C. Fellous, O. Kermarrec, Y. Campidelli, M. Laurens, M. Marty, J. Mourier, G. Troillard, A. Monroy, D. Dutartre, D. Bensahel, G. Vincent, and A. Chantre, “High performance 0.25 m SiGe and SiGe:C HBT’s using non selective epitaxy,” in Proc. BCTM, 2001, pp. 52–55. [8] M. Laurens, B. Martinet, O. Kermarrec, Y. Campidelli, F. Deléglise, D. Dutartre, G. Troillard, D. Gloria, J. Bonnouvrier, R. Beerkens, V. Rousset, F. Leverd, A. Chantre, and A. Monroy, “A 150 GHz f =f 0.13-m SiGe:C BiCMOS technology,” in Proc. BCTM, 2003, pp. 199–202. [9] S. Van Huylenbroeck, A. Subaja-Hernandez, A. Piontek, L. J. Choi, M. X. Xu, N. Ouassif, F. Vleugels, K. Van Wichelen, L. Witters, E. Kunnen, P. Leray, K. Devriendt, X. Shi, R. Loo, and S. Decoutere, “Lateral and vertical scaling of a QSA HBT for a 0.13-m 200 GHz SiGe:C BiCMOS technology,” in Proc. BCTM, 2004, pp. 229–232. 2032 [10] H. J. Osten, D. Knoll, B. Heinemann, H. Rücker, and B. Tillack, “Carbon doped SiGe heterojunction bipolar transistors for high frequency applications,” in Proc. BCTM, 1999, pp. 109–116. [11] J.-S. Rieh, B. Jagannathan, H. Chen, K. T. Schonenberg, D. Angell, A. Chinthakindi, J. Florkey, F. Golan, D. Greenberg, S.-J. Jeng, M. Khater, F. Pagette, C. Schnabel, P. Smith, A. Stricker, K. Vaed, R. Volant, D. Ahlgren, G. Freeman, K. Stein, and S. Subbanna, “SiGe HBT’s with cut-off frequency of 350 GHz,” in IEDM Tech. Dig., 2002, pp. 771–774. [12] M. Racanelli, K. Schuegraf, A. Kalburge, A. Kar-Roy, B. Shen, C. Hu, D. Chapek, D. Howard, D. Quon, F. Wang, G. U’ren, L. Lao, H. Tu, J. Zheng, J. Zhang, K. Bell, K. Yin, P. Joshi, S. Akhtar, S. Vo, T. Lee, W. Shi, and P. Kempf, “Ultra high speed SiGe NPN for advanced BiCMOS technology,” in IEDM Tech. Dig., 2001, pp. 336–339. [13] D. Ahlgren et al., “ Bipolar transistor with raised extrinsic base fabricated in an integrated BiCMOS circuit ,” U.S. Patent 6,492,238, Dec. 10, 2002. [14] M. Racanelli et al., “Method for fabricating a self-aligned emitter in a bipolar transistor,” Int. Patent Appl., Serial No. WO 02/43,132 A1, Nov. 19, 2001. [15] H. Schäfer, J. Böck, R. Stengl, H. Knapp, K. Aufinger, M. Wurzer, S. Boguth, M. Rest, R. Schreiter, and T. F. Meister, “Selective epitaxial growth of SiGe:C for high speed HBTs,” Appl. Surf. Sci., vol. 224, pp. 18–23, 2004. [16] S. Jouan, R. Planche, H. Baudry, P. Ribot, J. A. Chroboczek, D. Dutartre, D. Gloria, M. Laurens, P. Llinares, M. Marty, A. Monroy, C. Morin, R. Pantel, A. Perrotin, J. de Pontcharra, J. L. Regolini, G. Vincent, and A. Chantre, “A high-speed low 1/f noise in SiGe HBT technology using epitaxially-aligned polysilicon emitters,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1525–1530, Jul. 1999. [17] P. Chevalier, C. Fellous, B. Martinet, F. Leverd, F. Saguin, D. Dutartre, self-aligned SiGeC HBT using and A. Chantre, “180 GHz f and f selective epitaxial growth of the base,” in Proc. ESSDERC, 2003, pp. 299–302. [18] P. Chevalier, N. Zerounian, C. Fellous, L. Rubaldo, D. Dutartre, T. Jagueneau, F. Leverd, A. Perrotin, D. Gloria, B. Barbalat, F. Aniel, and A. SiGeC Chantre, “DC and HF characteristics of a 200 GHz f and f HBT technology at room and cryogenic temperatures,” in Proc. ISTDM, 2004, pp. 103–104. [19] B. Banerjee, S. Venkataraman, Y. Lu, S. Nuttinck, D. Heo, Y.-J. E. Chen, J. D. Cressler, J. Laskar, G. Freeman, and D. Ahlgren, “Cryogenic performance of a 200 GHz SiGe HBT technology,” in Proc. BCTM, 2003, pp. 171–173. [20] N. Zerounian, M. Rodriguez, M. Enciso, F. Aniel, P. Chevalier, B. Martinet, and A. Chantre, “Transit times of SiGe:C HBT’s using non selective base epitaxy,” Solid State Electron., vol. 48, pp. 2165–2174, 2004. [21] M. Schroter. (2001) HICUM, A Scalable Physics-Based Compact Bipolar Transistor Model. [Online]. Available: http://www.iee.et.tudresden.de/iee/eb [22] F. Ellinger, “26–42 GHz SOI CMOS low noise amplifier,” IEEE J. SolidState Circuits, vol. 39, no. 3, pp. 522–528, Mar. 2004. Pascal Chevalier was born in Saumur, France, in 1971. He received the engineering degree in science of materials from the University School of Engineers of Lille (Polytech’Lille), France, in 1994 and the Ph.D. degree in electronics from the University of Lille in 1998. He did his Ph.D. work at the Institute of Electronics, Microelectronics and Nanotechnologies (IEMN), Villeneuve d’Ascq, France. During his doctoral research, he worked in co-operation with Dassault Electronique (now Thales Aerospace) on the development of 0.1 m AlInAs/GaInAs InP-based HEMT technologies for low-noise and power millimeter-wave amplification. In 1999, he joined the Technology R&D department of Alcatel Microelectronics (now AMI Semiconductor), Oudenaarde (Belgian Flanders) as a Device and Integration Engineer to work on the development of 0.35 m Si BiCMOS technology. He was Project Leader for the development of 0.35 m SiGe BiCMOS technologies, developed in co-operation with the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium. In 2002, he joined the Advanced Bipolar Devices group of STMicroelectronics, Crolles, France, where he is currently Technical Leader in charge of the development of high-speed Si/SiGeC HBTs for advanced BiCMOS technologies. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 Cyril Fellous, photograph and biography not available at the time of publication. Laurent Rubaldo was born in Chalons sur Marne, France, in 1975. He received the engineering degree in physics of materials from the National Institute of Applied Science of Toulouse (INSAT, Engineering School), France, in 1997, and the Ph.D. degree in physics from the University Joseph Fourier of Grenoble, France, in 2001. He did his Ph.D. work at the High Magnetic Field Laboratory of CNRS Grenoble in collaboration with the Institute of Science and Technology of the Manchester University (UMIST), U.K. During his doctoral research, he participated in the development of a new generation of high-resolution Deep Level Transient Spectroscopy (DLTS): the Laplace DLTS (LDLTS). He studied deep levels in silicon and silicon alloys by LDLTS, combining magnetic field and uniaxial stress to investigate the electronic and structural properties of defects. In 2001, he joined STMicroelectronics, Crolles, France, in R&D Department as a Reliability Engineer to work on the study and modeling of new hot carrier mechanisms for submicron CMOS transistors and on the study of new aging mechanisms such as negative bias temperature instability (NBTI). In 2003, he joined the Front End Material R&D of the same company to work on the development of ultra-doped epitaxial Si and Si alloys for advanced bipolar devices, where he is currently in charge of the improvement of emitter materials for advanced HBT technologies. Franck Pourchon was born in Villeurbanne, France, in 1974. He received the M.S. degree in physics from the Ecole Nationale Superieure de Physique de Grenoble, France, in 1999. In 1999, he joined the Technology R&D Department of Alcatel Microelectronics (now AMI Semiconductor), Belgium, where he was involved in technology modeling for DMOS and BiCMOS technologies development. In 2001, he joined the Device Modeling group of STMicroelectronics, Crolles, France. He is currently in charge of transistor modeling for bipolar devices of advanced BiCMOS technologies. Sébastien Pruvost was born in Roubaix, France, on June 19, 1979. He received the M.S. degree in electronics from the Sciences and Technologies University of Lille, France, in 2001. He is currently working toward the Ph.D. degree at STMicroelectronics Crolles, France, in collaboration with IEMN (Institut d’Electronique, de Microélectronique et de Nanotechnologies), Villeneuve d’Ascq, France. His current research interests are millimeter-wave circuit designs for wireless communication using SiGe:C BiCMOS Technology. Rudy Beerkens received the B.Sc. degree in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1986. From 1986 to 2000, he was with Nortel Networks working in the areas of semiconductor manufacturing, BiCMOS process development, yield enhancement, device characterization, and reliability. In 2000, he joined STMicroelectronics, Ottawa, ON, Canada, to demonstrate benchmark circuits using high-performance SiGe-BiCMOS technologies. His scientific interests include high-speed broadband wireline and millimeter-wave integrated circuits. CHEVALIER et al.: 230-GHz SELF-ALIGNED SiGeC HBT FOR OPTICAL AND MILLIMETER-WAVE APPLICATIONS Fabienne Saguin was born in Besançon, France, in 1973. She received the engineering degree in electronic and microwave from the Ecole Nationale Supérieure d’Electronique et de Radioélectricite de Grenoble (ENSERG), France, in 1996. In 1996, she joined the HF characterization group of STMicroelectronics, Crolles, France, where she was involved in the HF characterization and modeling of passive devices. Since 1999, she has worked in the HF characterization of bipolar devices in small-signal, power, and HF noise domains. 2033 Didier Céli was born in Suresnes, France, on March 27, 1956. He graduated from Ecole Supérieure d’Electricité in 1981. In 1982, he joined the semiconductor division of Thomson-CSF, then the Central R&D of SGS-Thomson Microelectronics, now STMicroelectronics, Crolles, France. He has worked in the field of modeling for advanced Bipolar and BiCMOS technologies, including model development, parameter measurement and extraction tools. Presently, he is responsible for BiCMOS device modeling as project manager. Nicolas Zerounian graduated from the Ecole Normale Supérieure de Cachan, France, in 1995 and received the Ph.D. degree in electrical engineering from Université Paris Sud 11 (UP11), Orsay, France, in 2000. Since 2002, he has been with UP11 as an Associate Professor. His research interests are characterization and modeling of high speed devices in IV-IV and III-V compound semiconductors at room and low temperature. Benoît Barbalat was born in Boulogne-Billancourt, France, in 1980. He received the engineering degree in electrical engineering from the Ecole Supérieure d’Electricité (Supélec), Gif-sur-Yvette, France, in 2003 and the M.S. degree in device physics from the University of Grenoble, France, in 2004. He is now working toward the PhD degree in microelectronics in the Advanced Bipolar Group of STMicrolectronics, Crolles, France, in collaboration with the Institute of Fundamental Electronics (IEF) from the University of Paris 11, Orsay. His doctoral research focuses on the physics and optimization of high-speed SiGeC HBTs. Sylvie Lepilliet was born in Béthune, France, on May 20, 1964. In 1986, she joined the Centre Hyperfréquences et Semiconducteurs, University of Lille, France. She is now in charge of high-frequency measurement facilities of IEMN and more especially of the noise test set. Didier Dutartre was born in 1956. He received the engineering degree in material physics from the Institut des Sciences Appliquées de Lyon, France, in 1979, and the Ph.D. degree in 1983. His doctoral research dealt with thermodynamics and liquid phase epitaxy of III-V compounds. In 1983, he joined the Centre National d’Etudes des Télécommunications (CNET) as a Researcher in material science. From 1983 to 1989, he developed the lamp zone melting recrystallization technique for the fabrication of thin silicon on insulator films. Between 1989 and 1994, he worked in reduced pressure rapid thermal CVD and started the CNET research activities on SiGe epitaxy. In 1994, he joined the Centre Commun Crolles, a consortium between CNET and STMicroelectronics, where he developed high-temperature Si epitaxy, in situ doped Si poly processes, and low-temperature Si/SiGe epitaxy. In 1999, he joined STMicrolectronics, Crolles, France, where he is presently leading R&D activities in front end materials. He holds more than 20 patents and has about 100 publications in these fields. Isabelle Telliez received the engineering degree from Ecole Centrale de Lyon, France in 1985. From 1985 to 1987, she worked at Thomson Composants Microondes toward the Ph.D. degree on large-signal FET modeling and power amplifier design. She then joined Thomson Composants Microondes, now U.M.S., where she was involved in MMIC designs on GaAs more particularly for direct demodulation receivers and high efficiency power amplifiers for T/R modules. She has joined STMicroelectronics, Crolles, France, in 1997, where she is involved in microwave and millimeter-wave designs for wireless applications such as 5 GHz WLAN, UWB, and SerDes. She is currently a RF/Microwave design group leader. Daniel Gloria received the engineering degree in electronics from the Ecole Nationale Supérieure d’Electronique et de Radioélectricité in 1995, and the M.S.E.E. degree in optics, optoelectronics and microwaves design systems from the National Polytechnical Institute of Grenoble (INPG), France. He spent two years, from 1995 to 1997, in ALCATEL Bell Network System Labs, Charleroi, Belgium, as an RF Design Engineer and was involved in the development of the Cablephone RF front end and its integration in hybrid-fiber-coax telecommunication networks. Since 1997, he has been working for ST Microelectronics, Central R&D, Crolles, as a High Frequency (HF) Research Engineer. His interests are in optimization of active and passives devices for HF applications in BiCMOS and CMOS advanced technologies. Frédéric Aniel (M’03) received the Ph.D. degree from Université Paris-Sud (UPS), France, in 1994. He worked on circuit design at Aerospatiale in 1991 and on device development at France-Telecom CNET in 1995. He is Associate Professor at UPS since 1996 and currently heads an IEF research team on the analysis of physical phenomena in very high frequency devices. His research activities are mainly on heterojunction transistor physics, first III-V devices, and more recently SiGe alloy devices. His emphasis is on device high frequency and optical characterizations both at 300 K and at low temperatures supported by physical and electrical modeling. 2034 François Danneville (M’98) was nominated Associate Professor of the University of Lille, France, in 1991. Over the last ten years, his research has been carried out at the Institut d’Electronique, de Microélectronique et de Nanotechnologie (IEMN), France, where he has studied the noise properties of III-V devices operating in linear and non linear regime, for application in centrimetric and millimetric range. In 1998, he held a position of Visitor (noise expertise) in Hewlett-Packard (now Agilent) EEsof Division, Santa Rosa, CA. Since 2001, he has been a Full Professor at University of Lille. He gives courses in compound semiconductor device physics, noise in devices, linear and nonlinear electronics intended to analog, microwave and numerical circuits (third and fourth years university level). His research at IEMN is oriented toward advanced silicon devices and circuits, which includes the dynamic, noise and linearity properties of MOSFETs based devices (including alternative architectures), SiGe HBT and circuit design in millimetric wave range using SOI Technology and SiGe BiCMOS Technology. He has authored or co-authored about 80 scientific international publications and communications. He holds the positions of Editor for the Fluctuation and Noise Letters Journal, Chairman of the Microwave Low Noise and Techniques MTT-14 Technical Committee, IEEE MICROWAVE THEORY AND TECHNIQUES. He has been the Member of several International Scientific or TP Committees (UPoN ’99-Adelaide, SPIE FaN 2003-Santa Fe, ICNF 2003-Prague, ICCDCS 2004). He was also the Chairman of Noise in Devices and Circuits Conference, SPIE Fluctuations and Noise Symposium, 2004, Canary Islands, and will be the Co-Chairman of the next one in 2005, in Austin, TX. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 10, OCTOBER 2005 Alain Chantre (M’91–SM’97) was born in Reims, France, in 1953. He received the engineering degree in physics from the Institut National des Sciences Appliquées de Lyon, France, in 1976, and the Ph.D. degree from the Université Scientifique et Médicale de Grenoble, France, in 1979. His doctoral research concerned deep level optical spectroscopy (DLOS) in GaAs. He joined the Centre National d’Etudes des Télécommunications (CNET), Grenoble, in 1979. He worked from 1979 to 1985 at the CNET Grenoble laboratory and during 1985–1986 at AT&T Bell Laboratories, Murray Hill, NJ, on deep level defects in silicon. From 1986 to 1992, he was in charge of a group working on the characterization of advanced silicon processes and devices. From 1993 to 1999, he has been working within the GRESSI consortium between France Telecom CNET and CEA-LETI, as head of a group involved in the development of advanced bipolar devices for submicron BiCMOS technologies. He joined STMicroelectronics, Crolles, in 2000, where he is currently managing the development of advanced SiGe bipolar devices and technology for RF and optical communications applications. He has published over 130 technical papers related to his research, and holds 20 patents.