Design procedures of bipolar low noise amplifier at radio frequency using s parameters

Design procedures of bipolar Low Noise Amplifier (LNA) at Radio Frequency (RF)
Using S-Parameters
Mohamed Abdultawab Abdulla
Department Of Electronics and Communication, Faculty Of Engineering, Aden
University
Abstract
This paper presents an easy look at the design procedures of how to design
RF amplifier Class (A) where S-parameters of the transistor is used with a
specialized RF design tool. The purpose of this paper is very useful for students to
know the design procedures at radio frequency. It provide the academic students
in the faculty of electronics and communication engineering with modern design
tools and techniques, and enhance their learning by stimulating their mind
through the design practice. As a result, students to be an electronic engineer will
have first hand experiences and an academic proficiency in the field of RF design
and simulation, with an understanding for subject content.
Keywords: BJT, RF, LNA, Amplifier, Design,
I) Introduction
As radio frequency (RF), low noise amplifier (LNA) design is more
complicated than other amplifier design. It is a step-by-step logical procedure with
an exact solution for each problem. It may require minimum noise, maximum
gain, best impedance matching, stability, and other performance factors. These
can be expressed either in terms of the two-port S-parameters of the device or the
component values of an equivalent circuit.
In this paper we look at how to do the design an RF amplifier, based on Sparameters of an RF bipolar transistor.
The design procedure involves several fundament steps:
1) obtain the most important design specifications.
2) selection of the transistors, according to design specifications.
3) both dc and ac characterization of the transistors, such as fT, β (dc and
ac).
4) selection a proper operating point,

5) Check the transistor’s parameters for the selected operating point,
The block diagram was given in Fig.1, which consists the source, transistor,
dc bias, matching network, and the load.

Figure 1. block diagram of typical amplifier design
This paper was distributed into four sections as follows:
1) Introduction,
2) Design procedures, was divided to the following subsections:
1- Choice of transistor:
2- DC Bias network:
3- Transistor stability:
4- Source and load matching:
5- Gain and Noise in amplifier.
3) S-parameters simulation
4) Conclusion.
5) References.

II) Design procedures
1-

Choice of transistor:

Choosing a transistor for an RF amplifier is more complicated than
choosing it for other application. It involves choosing one in the right package
having an adequate current rating, with gain and noise figure capability that meets
the requirements of the intended application. It is also important that the selecting
of a transistor has breakdown voltages which will not be exceeded by the dc and RF
voltages that appear across the various junctions of the transistor and that permit
the gain at frequency objectives to be met by the transistor.
A first step for the choice of transistor is to decide the frequency range,
because it may affect other specifications. To make a choice of transistor we will
need to consult the tables of technical data which contain a great deal of useful
information. Understanding data sheet specifications can help selecting and using
RF devices for specific application. It describe the transistor's behavior at RF
frequencies.

Figure 2. A) Gain G = f (VCE), IC = Parameter,
B) Transition frequency fT = f (IC), VCE = Parameter
The parameters found in the device data sheet typically are: S-parameters,
MAG (Maximum Available Gain), and Rollet factor (k). These parameters allow a
first feasibility analysis of the design with a specific transistor. Other parameters
are the current gain (β), and the cutoff frequency (fT), include a plot of G versus
VCE and ft versus collector current. The last curve will increase with current, flatten
and then begin to decrease as IC increases thereby revealing useful information
about the optimum current with which to achieve maximum device gain (Figure
2).

The most important properties to look for are the maximum collector
current IC and the current gain.
Transistor selection and examination of its data
From the technical data sheet of Infineon, BFP640 SOT 343 npn Silicon
Germanium bipolar transistor was selected, It is ideal for RF designs, with
excellent low-noise and high gain characteristics.
Table 1 Electrical Characteristics of BFP640
Gma = IS21e/S12eI (K-(K2-1)1/2), Gms = IS21e/S12eI
Values
Unit
Parameter
Symbol
min. typ. max.
Transition Frequency
fT
30
40
GHz
IC = 30 Ma, VCE = 3 V, f = 1GHz
Noise figure ZS=ZSopt
F
0.65
dB
IC = 5 Ma, VCE = 3 V, f = 1.8 GHz
Max. Power gain, stable
IC = 30mA, VCE =3 V, f = 1.8 GHz
Gms
24
dB
ZS = ZSopt, ZL = ZLopt
Max. Power gain, available
Gma
12.5
dB
IC = 30mA, VCE = 3V, f = 1.8 GHz
ZS = ZSopt, ZL = ZLopt
Transducer gain ZS =ZL =50Ω
21
dB
IS21eI2
IC = 30mA, VCE = 3 V, f = 1.8 GHz
Values
Unit
DC Characteristics Parameter
Symbol
min. typ. Max.
Collector-emitter breakdown voltage IC =
V(BR)CEO
4
4.5
V
1Ma, IB = 0
Collector-emitter cutoff current
30
µA
ICES
VCE = 13V, VBE = 0
Collector-base cutoff current
100
nA
ICBO
VCB = 5V, IE = 0
Emitter-base cutoff current
3
µA
IEBO
VEB = 0.5V, IC = 0
DC current gain
hFE
100 180 320
IC = 30 Ma, VCE = 3V
Table 1 shows the electrical and DC characteristics of the transistor. The
maximum ratings are: VCEO = 4 V, VCES = 13 V, VCBO = 13 V, VEBO = 1.2 V, IC = 50
mA, IB = 3 mA, Ptot = 200 mW.
In figures 3 and 4 With a typical operating voltage VCE of 3 V and an
operating current IC of 30 mA, the gain is above 22 dB whereas the NF is below 1.2
dB for 0.9 GHz and 1.8 GHz. They also show that the gain is increasing whereas
the NF is reducing with respect to IC, respectively.

Figure 3. Power gain Gma, ms = f (IC, f). High maximum stable gain Gms = 24 dB at IC =
30 mA, VCE = 3V, f =1.8 GHz

Figure 4. Noise figure F = f (IC), VCE = 3 V, f = 1.8 GHz; F = 1.1 dB at IC = 30 mA,
VCE = 3 V, f =1.8 GHz

Figure 5: Package Parasitic Characteristics of BFP640

Figure 5 shows the package parasitic characteristics of the BFP640
transistor, and table 2 shows the transistor parameters used in the Gummel - Poon
model for the same transistor. Chip parasitics and Package Model SOT 343 for
BFP640 are in table 3 and 4.
Table 2 Gummel - Poon model, SOT 343 for BFP640
1
4
7
10
13
16
19
22
25
28
31
34
37
40

IS
NF
BF
NE
ISE
NR
BR
NC
ISC
VAF
VAR
IKF
IKR
TNM

0.2 fA
1.025
450
2
21 fA
1
55
1.8
400 fA
1000 V
2
0.15 A
3.8 mA
25

2
XTI
3
3
EG
5
TF
1.8 pSec
6
KF
8
VTF
1.5 V
9
XTB
11
XTF
10
12
AF
14
ITF
0.4 A
15
RC
17
CJE
227.6 fF
18
PTF
20
VJE
0.8 V
21
RE
23
MJE
0.3
24
TR
26
CJC
67.4 fF
27
IRB
29
VJC
0.6 V
30
FC
32
MJC
0.5
33
RBM
35
XCJC
1
36
MJS
38
CJS
93.4 fF
39
RB
41
VJS
0.6 V
Table 3 Chip parasitics BFP640

CHIP

C

B

E

SUBCKT CHIP

1

2

3

X1 SOT343

22

11

33

X2 CHIP

11

22

33

Q1

10

20

30

20

30

1.078
7.2E-11
1.42
2
3.061
0
0.6
0.2 nSec
1.52 mA
0.8
2.707
0.27
3.129

CBEC
CBCC

10

LBC
LCC

2

1

4
9.840E-14

20

5.593E-14

20
10

3

2
1.200E-10

1.200E-10
1

LEC

30

2.000E-11

3

CES

33

1.800E-13

3

CBS

22

2

7.900E-14

CCS

11

7.500E-14

RBS

22

4

1.200E+03

4

1.200E+03

RCS
RES

11
33

1

3.000E+02

3

Table 4 Package Model SOT 343 for BFP640
SOT343

Bi

Ci

Ei

Bo

Co

Eo

SUBCKT

1

2

3

10

20

30

LBB

1

10

0.6962E-9

LCB

2

20

0.6824E-9

LEB

3

30

0.2306E-9

CCEO

131.2E-15

CBEO

102.5E-15

CCEI

10
2

CBEI
2-

20

1

30
30

3

112.6E-15

3

180.4E-15

dc biasing:

Biasing a Transistor amplifier is the process of setting the dc (Biasing)
operating voltage and current to the correct level so that any ac input signal can be
amplified correctly by the transistor. That is by setting its Collector current (IC) to
a steady state value without an input signal applied to the transistors Base, and by
the values of the dc supply voltage (VCC) and the value of the biasing resistors
connected the transistors Base terminal. The goal was to select an operating point
that would give sufficient output power, have relatively low noise, and operate in
the class A region.
The correct bias Operating point of the transistor is generally somewhere
between the two extremes of operation, that is halfway between cutoff and
saturation. This mode of operation allows the output current to increase and
decrease around the amplifiers Q-point without distortion as the input signal
swings through a complete cycle.
Figure 6 shows the simulation test bench of how the BFP640 was evaluated.
Figure 7 shows (IV curve), the collector-emitter voltage (VCE) versus the collector
current (IC) of the device. They are convenient for creating the transfer
characteristics of the device and also for finding the voltage of the base-emitter
junction (VBE) for a specified base current (IB). From the base current versus base
voltage plot we can find out what kind of quiescent base voltage we need from our
bias network.

GBJT
ID=GP1

IVCURVEI

ID=IV1
VSWEEP_start=0 V
VSWEEP_stop=5 V
VSWEEP_step=1 V
ISTEP_start=8e-7 mA
ISTEP_stop=0.3 mA
ISTEP_step=0.025 mA

2

4
S

1
B

Swp

Step

C

3

E

Figure 6 Establishing the dc transfer characteristics and finding the dc bias
parameters

Figure 7 The dc transfer characteristics of the BFP640 Transistor.
Biasing Considerations for BJT RF Transistors:
Bias network is one of the factors need to be considered in RF transistor
amplifier design. It provides the required working conditions for the chosen
transistor. In term of the chosen dc bias, a compromise of the various specification
targets had to be made. The bias circuit must simultaneously ensure a stable
operating point and a certain isolation of the RF stage.
For good gain characteristics, it is necessary to bias the transistor at
collector current (IC) that results in maximum or near-maximum transition
frequency (fT). On the other hand, for best noise characteristics, a low current is
generally most desirable.
The scattering (S) Parameters, is one of the most useful means of specifying a
linear device, which are voltage reflection and transmission coefficients when the
device is embedded into a 50 Ω system.

|S11|, the magnitude of the input reflection coefficient is directly related to
input VSWR = (1 + |S11|) / (1 – |S11|).
|S22|, the magnitude of the output reflection coefficient is directly related to
output VSWR.
|S21|2 is the power gain of the device when the source and load impedances
are 50 Ω.
By biasing the transistor according to the measured specifications and Sparameter, appropriate amplifier S-parameters can be achieved. With these
parameters, we can calculate potential instabilities, maximum available gain
(GAVmax), input and output impedances (Zin, Zo) and transducer gain (GT).
Maximum Unilateral (S12 = 0) Gain, (GUmax) is the 50 Ω gain increased by a
factor which represents matching the input and increased again by a factor which
represents matching the output. GUmax = |S21|2 / {(1 – |S11|2 (1 – |S22|2)}.
Once selected the transistor and the bias operating point, the next step is
the design of the bias stage.
Design of The Biasing Circuit
The dc bias point were chosen to be 3 V at 30 mA to achieve the desired
goals. It gives the best gain and a reasonably good noise figure. Note that the Sparameters, as well as other RF parameters, are all bias dependent. If the bias
conditions change significantly, the performance will also change. To illustrate the
resistive dc bias network, we use the AppCAD program from Agilent, with resistive
feedback networks.

Figure 8 AppCAD solution for the dc bias

The Collector Feedback Biasing configuration shown in Figure 8, ensures
that the transistor is always biased in the active region regardless of the value of
(β). The Base bias IB is derived from the Collector voltage VCE. A fraction of the
collector signal is introduced back to the base circuit. This is most easily done via
the positive biasing resistor (RB1). The second resistor in the base circuit (RB2)
permits a portion of the current flowing through RB1 to bypass the base. If the
Collector current increases, the Collector voltage drops, reducing the Base drive
and thereby automatically reducing the Collector current. In this amplifier, the
bias is derived by a feedback circuit that controls the base current to stabilize the
collector current at a specific level.
For dc stability, it is a good practice to run about 5% to 10% of the collector current through the resistive base-voltage divider. RB2/RB1 ratio is usually
between 0.5 to 0.75. RB1 is usually bigger.
Transistor Biasing Procedure
Step 1: Choose a Target VCE: Using collector resistor RC.
The transistor needs to work under proper dc conditions, which are
provided by the biasing design. Figure 8 shows the biasing circuit used in this
work. Since we will use the device with S-parameters measured at VCE = 3 V (ruleof-thumb 40% of VCC) and IC = 30 mA, setting our supply voltage VCC to 7.5 V,
(VBE = 0.879 V, β = 100).
Step 2: Choose RB1 and RB2 to bias the npn.

V
879 mV
I RB 2 = BE =
= 2.93mA
RB 2
300
V − VBE (3 ,000 − 879 ) mV
I RB 1 = CE
=
= 3.4 mA
RB 1
620
Step 3: Choose RC.

V − VCE (7.5 − 3 )V
I RC = CC
=
= 34.6 mA
RC
13O
IC = IRC - IRB1=34.6 - 3.4 = 30.2 mA
IB = IC/hFE = 30.2/100 = 0.302 mA
The current flowing through resistor RB1 is shared by both resistor RB2 and
the emitter base junction VBE. The greater the current through resistor RB2, the

greater the regulation of the emitter base voltage VBE.
In the case of the bias network that uses voltage VRB2 feedback with current
source, the designer must pick the voltage across RB2 and the bias current IRB2
through resistor RB2.
The available values of the obtained resistors are listed in Table 5.
Table 5 Resistors with available values of the biasing design
IRC

RC

RB1

RB2

IC @ hFE100; C25

34.6

130

620

300

33.8

3- Transistor stability:
The stability of an amplifier, is a very important consideration in a design
and can be determined from the S-parameters, the matching networks, and the
terminations.
The case where the transistor is unconditionally stable:
The first thing to worry about with a transistor at radio frequency (RF) is
stability. Two main methods exist in S-parameter stability analysis: numerical and
graphical.
A- Numerical analysis consists of calculating a term called Rollett Stability
Factor (K) which represents a quick check for stability at given frequency and
given bias condition.
In making stability calculations using measured S-parameters, one must
bear in mind that the reverse transmission coefficient (S12) of high-transition
frequency devices like the BFP640 becomes vanishingly small at lower frequencies.
One method to improve the stability is to resistively load the input or output of the
amplifier.
If the input is resistively loaded then the noise figure will degrade.
If the output is resistively loaded, then the gain will be reduced.
Rollet Stability Factor, K is derived as follows:
2

2

1 − S11 − S22 + Δ
K=
2 − S12S21

2
(1)

A sweep of the K-factor over frequency for a given biasing point should be
performed in order to assure unconditional stability outside of the band of
operation (∆ = S11 S22 – S12 S21). If K > 1 and |∆| < 1, then the device will be

unconditionally stable for any combination of source and load impedances. For K <
1 the device is potentially unstable. If that’s the case, we must choose source and
load impedances very carefully or select another bias point or choose a different
transistor.
An alternative form is K > 1 and B1 > 0 where,
2

B1 = 1 + S11 − S22

2

(2)

or the necessary and sufficient condition for unconditional stability is the stability
factor µ1 > 1 where,

1 − S 11

μ1 =

2
(3)

S 22 − S 21 * det ( S ) + S 21 S 12

B- A graphical method is used to determine the stability conditions of the
transistor in Smith chart. The requirements for stability are the values of the
reflection indexes (Γ) at the input |Γin| < 1 or at the output |Γout| < 1. These are
defined by stability circles, that delimit |Γin| = 1 and |ΓL| = 1 on the Smith chart.
4-

Matching network and Gain:

The last step is to take the values of the reflection coefficients at the input
and the output, and to design for these values their corresponding input and
output matching couplers. Input and output return losses (S11 and S22 respectively)
are important properties in RF circuits, because they will affect the gain and noise
figures and tell about how well the circuit is matched. The lower S11 and S22 are,
the better is the matching. An improvement in gain can always be achieved by
matching the device’s input and output impedances to 50 Ω by means of matching
networks.
The transducer power gain GT includes the effects of input and output
impedance matching and can be expressed as the product of three gain
contributions GT = GS GO GL, where:

GS =

1 − ΓS

2

1 − ΓinΓS

2

2

and G0 = S21 and GL =

1 − ΓL

2

1 − S22ΓL

2

2

2

2

2

1 − ΓS
1− ΓS
P
2 1− ΓL
2 1 − ΓL
S21
=
S21
GT = L =
2
2
2
Pavs 1− Γ Γ 2
1− S22ΓL
1 − S11ΓS
1 − ΓoutΓL
in S
2

2

=

2

S21 ( 1 − Γ S )( 1 − Γ L )
( 1 − S11Γ S )( 1 − S22Γ L ) − ( S12S21Γ LΓ S

(4)

2

We see that GT is a function of the source and load terminations (ΓS and ΓL)
and of the S-parameters of the two-port shown in Figure 9. If we know all those
parameters, the gain computation is quite straightforward.

Figure 9 (a) In maximum gain amplifiers the actual source and load terminations Z1
and Z2 are transformed to ΓMs and ΓML. (b) placing the unconditionally stable twoport between ΓMs and ΓML matches the amplifier to Z1 and Z2.
If the amplifier is to produce the maximum small-signal power gain
available from the active device, we must find a unique solution for two
terminations to impedance-match both ports simultaneously, ΓS = ΓMS and ΓL =

ΓML. Then we realize the simultaneously conjugate matched maximum gain, called
GMAX.
G MAX =

S 21 ⎛
⎜K −
S 12 ⎝

K 2 − 1⎞
⎟
⎠

(5)

Equation (5) is valid for unconditionally stable two-ports only. For a
potentially unstable device, we define the maximum stable gain (MSG), after the
device is stabilized with cascaded resistance to borderline stability, that is, to
achieve K =1.
MSG =

5-

S 21
S 12

(6)

Noise in Amplifier:

The transistor will add noise, then be amplified by the hFE of the device just as

the signal is, forming signal plus noise output S+N. Noise figure (NF) is a measure of
the degradation in signal-to-noise ratio (SNR) between the input and output ports
of an active network. The excess in the S+N to signal power is due to the noise figure
(NF) of the device. NFmin is defined as the minimum noise figure that can be
achieved with the transistor.
To achieve this NF requires source impedance matching which is usually
different from that required to achieve maximum gain. The design of a low noise
amplifier, then, is always a compromise between gain and NF. A useful tool to aid in
this compromise is a Smith Chart plot of constant gain and Noise Figure contours
which can be drawn for specific operating conditions typically bias and frequency.
These contours are circles which are either totally or partially complete within the
confines of the Smith Chart. If the gain circles are contained entirely within the
Smith Chart, then the device is unconditionally stable. If portions of the gain
circles are outside the Smith Chart, then the device is considered to be
“conditionally stable” and the device designer must concern himself with
instabilities, particularly outside the normal frequency range of operation.
If the data sheet includes Noise Parameters, a value will be given for the
optimum input reflection coefficient (ΓOPT) to achieve minimum noise figure. But
remember if you match this value of input reflection coefficient you are likely to
have far less gain than is achievable by the transistor. The input reflection
coefficient for maximum gain is normally called ΓMS, while the output reflection
coefficient for maximum gain is normally called ΓML.
Another important noise parameter is noise resistance (Rn). Sometimes in
tabular form, you may see this value normalized to 50 ohms in which case it is
designated rn. The significance of rn can be seen in the formula below which
determines noise figure NF of a transistor for any source reflection coefficient ΓS if
the three noise parameters - NFmin, rn and ΓO are known.

NF = NFmin + {4rn |ΓS – ΓO|2} / {(1 – |ΓS|2) |1 + ΓO|2}. (7)
By choosing different values of NF one can plot a series of noise circles on
the Smith Chart. Incidentally, rn can be measured by measuring noise figure for ΓS
= 0 and applying the equation stated above.
Noise factor, F is the numerical ration of noise figure where it can be

expressed in dB. Thus, the noise figure is:

NF = 10 log10 F , and F = Input SNR

Output SNR

(8)

The noise figure of an amplifier generally varies as:

F = Fmin +

RN

ΓS

Y S − Yopt

2

(9)

where:

Ys - the source admittance presented to the transistor
YOPT - the optimum source admittance that results in minimum noise figure
Fmin - the minimum noise figure
Rn - the equivalent noise resistance of the transistor, and
ΓS - the real part of Ys
The Noise Figure of the completed amplifier is equal to the Noise Figure of
the device plus the losses of the matching network preceding the device. The Noise
Figure of the device is equal to Fmin only when the device is presented with Γopt. If
the reflection coefficient of the matching network is other than Γopt, then the Noise
Figure of the device will be greater than Fmin.

S-parameters Simulation:

III)

Simulation tools are an invaluable design aid which allow concepts to be
tried out without having to spend many hours trying to coax a physical circuit into
operation. They are also very useful as a learning tool and allow us to quickly see
the effects of changing various circuit components in an otherwise working design.
We first use the data sheet S-parameters of the BFP640, without any
stabilization (Table 6), and compute MSG in decibels. Then, we compare MSG
with GMAX of the stabilized device.
Without stabilization the device has basic transducer power gain of

10 log S 21

2

= 20.9 dB . Angles are given in degrees. Transistor data sheets

show MSG at frequencies where the device is potentially unstable and GMAX at
other frequencies. Computing MSG from the above S-parameters at 1.9 GHz gives
us:

MSGdB = 10 log

S 21
⎛ 11.1 ⎞
= 10 log ⎜
⎟ = 23.46 dB
S 12
⎝ 0.05 ⎠

Table 6: Infineon Technologies Discrete & RF Semiconductors BFP640,

VCE = 3.0 V, IC = 30 mA Common Emitter S-Parameters: Sep 2002
Frequency

S11

S11

S12

S12

S21

S21

S22

S22

GHz

MAG

ANG.

MAG

ANG.

MAG

ANG.

MAG

ANG.

1

0.34

-109.6

0.03

61.1

19.66

101.7

0.49

-45.1

1.1

0.32

-115.4

0.03

60.7

18.11

99

0.46

-45.6

1.2

0.31

-120.7

0.04

60.3

16.8

96.7

0.44

-45.9

1.3

0.29

-125.7

0.04

59.9

15.67

94.7

0.42

-46

1.4

0.28

-130.5

0.04

59.6

14.69

92.6

0.4

-46.1

1.5

0.27

-135.2

0.04

59.2

13.81

90.4

0.39

-46.2

1.6

0.27

-139.8

0.04

58.8

13.03

88.2

0.38

-46.4

1.7

0.26

-144.3

0.05

58.3

12.33

85.8

0.36

-46.5

1.8

0.26

-148.6

0.05

57.9

11.69

83.4

0.35

-46.7

1.9

0.25

-152.6

0.05

57.4

11.1

81.1

0.34

-46.8

2

0.25

-156.4

0.05

56.9

10.57

79.2

0.33

-46.9

2.1

0.25

-159.8

0.05

56.4

10.08

77.68

0.33

-46.9

2.2

0.24

-163.1

0.06

55.9

9.63

76.5

0.32

-46.9

2.3

0.24

-166.1

0.06

55.41

9.22

75.61

0.32

-46.8

2.4

0.24

-169.2

0.06

54.9

8.85

74.8

0.31

-46.9

The overall performance of a low noise amplifier is determined by
calculating the transducer gain GT, noise figure NF and the input and output
standing wave ratios. The optimum ΓL was obtained as ΓL = 0.4492 + j 0.677. The
value of ΓL was selected on the 11 dB circle, which corresponds to a noise figure of
2.5 dB.
As we will see in Table 7, GMAX at 1.9 GHz is 18.2 dB and is 5.1 dB less than
the initial MSG of the device.

Table 7 Stabilized S-Parameters of the BFP 640, biased At 3 V and 30 mA
Frequency

S11

S11

S21

S21

S12

S12

S22

S22

(GHz)

MAG

ANG

MAG

ANG

MAG

ANG

MAG

ANG

1.8

0.28

-82

6.63

76

0.060

70

0.49

4.8

1.9

0.25

-92

6.64

72

0.066

67

0.51

-1.7

Frequency

µ

S21

Gmax

ΓMS

ΓMS

GML

GML

(GHz)

factor

dB

dB

MAG

ANG

MAG

ANG

1.8

1.18

16.4

17.9

0.28

145

0.55

6.42

1.9

1.09

16.4

18.2

0.41

166

0.65

13.6

If this stable two-port is simultaneously terminated with ΓMS and Γag the gain at 1.9
GHz is Gmax = 18.2 dB.
A graphical method is used to determine the stability conditions of the
transistor. The input and output stability circles are plotted using Ansoft Designer
Suite for the transistor S-parameters. A frequency sweep from 1.5GHz to 3.5GHz
is applied to check for unwanted oscillations around the operating frequency of
2.4-2.5GHz.
From figure 10, we see that both the input and output stability circles lie
completely outside the Smith Chart for the range of frequencies 1.5 GHz to
3.5GHz; hence the transistor is unconditionally stable for the frequency range.

Figure 10. Input and Output Stability Circles
Once the stable regions on the smith chart have been determined, another
graphical method is used to choose a particular gain and noise figure. Desired gain
and noise figure can be obtained with proper selection of the reflection coefficient

of the input and output matching networks. We select an optimum ΓL point on the
smith chart out of a random selection of ΓL points by checking for the best return
loss performance.

Figure 11. Gain, Noise and Stability Circles at 2.4 GHz
As shown in the diagram, input and output is quite stable at the frequency
range of 88 MHz to 108 MHz, that is, 27.5 dB to 25 dB in this frequency range,
which is 5 dB on average higher than |S21|2.
Choosing the matching network topologies is the next step.
IV) Conclusion:
The paper offers a step-by-step logical procedure of how to design an RF
amplifier Class (A) in terms of S-parameters of the transistor with a specialized RF
design tool.
We are used BFP640 from Infineon as an active two-port device and
characterize it in terms of S-parameters.
We are selected the bias operating point, calculating the bias network to
provides the required working conditions for the chosen transistor, checking it for
stability, deciding the working current.
We are using a different Simulation tools as an invaluable design aid allows
us to quickly see the effects of changing.

V) References:

[1] Agilent

Technologies 2000. "Application Note 1190 - Low Noise

Amplifier for 900 MHz using the Agilent ATF-34143.
[2] AppCAD Software Informer from Agilent. http://www.hp.woodshot.com.
[3] http://www.awrcorp.com/products/microwave-office.
[4] Infineon Technologies May 2007, Datasheet of BFP640, Silicon
Germanium Transistor. www.infineon.com.
[5] Pozar D. 2005, Microwave Engineering. 2nd edition, John Wiley and
Sons.
[6] Sischka F. Jun. 2001, "Gummel-Poon Bipolar Model, Model Description,
Parameter Extraction." Agilent Technologies, http://www.home.agilent.com.
[7] Sungkyung P. and Wonchan K. Feb 2001 "Design of A 1.8 GHz Low-noise
Amplifier For RF Front-end in A 0.8um CMOS Technology", IEEE Transactions on
Consumer Electronics, Volume: 47 Issue: 1.

‫اﺟﺮاءات ﺗﺼﻤﻴﻢ ﻣﻜﺒﺮ ﻋﻤﻠﻴﺎت ﺛﻨﺎﺋﻲ اﻟﻘﻄﺒﻴﺔ ﻣﻨﺨﻔﺾ اﻟﻀﻮﺿﺎء ﻋﻨﺪ ﺗﺮددات ﻓﺎﺋﻘﺔ اﻟﺴﺮﻋﺔ ﺑﺎﺳﺘﺨﺪام ﻣﻌﺎﻣﻼت‬
‫اس.‬
‫ﻣﻠﺨﺺ‬
‫ﺗﻌﺮض هﺬﻩ اﻟﻮرﻗﺔ ﻃﺮﻳﻘﺔ ﻣﺒﺴﻄﺔ ﻻﺟﺮاءات ﺗﺼﻤﻴﻢ ﻣﻜﺒﺮ ﻳﻌﻤﻞ ﻋﻨﺪ ﺗﺮددات ﻓﺎﺋﻘﺔ اﻟﺴﺮﻋﺔ، ﺑﺎﺳﺘﺨﺪام‬
‫ﻣﻌﺎﻣﻼت اس ﻟﻠﺘﺮاﻧﺰﻳﺴﺘﻮر وادوات ﺗﺼﻤﻴﻢ ﺗﺨﺼﺼﻴﺔ. ان هﺪف هﺬﻩ اﻟﻮرﻗﺔ ﻣﻔﻴﺪ ﺟﺪا ﻟﻠﻄﻼب ﻓﻲ ﻣﻌﺮﻓﺔ اﺟﺮاءات‬
‫اﻟﺘﺼﻤﻴﻢ ﻋﻨﺪ ذﺑﺬﺑﺔ اﻻرﺳﺎل ﻓﺎﺋﻘﺔ اﻟﺴﺮﻋﺔ، وﻳﺰود اﻟﻄﺎﻟﺐ اﻻآﺎدﻳﻤﻲ ﻓﻲ آﻠﻴﺎت اﻟﻬﻨﺪﺳﺔ اﻻﻟﻜﺘﺮوﻧﻴﺔ واﻻﺗﺼﺎﻻت‬
‫ﺑﺘﻘﻨﻴﺎت اﺳﺘﺨﺪام ادوات اﻟﺘﺼﻤﻴﻢ اﻟﺤﺪﻳﺜﺔ، وﻳﺤﺴﻦ ﺗﻌﻠﻤﻬﻢ ﺑﺘﺤﻔﻴﺰ اﻟﻌﻘﻞ ﻋﺒﺮ ﻣﻤﺎرﺳﺔ اﻟﺘﺼﻤﻴﻢ. ﻧﺘﻴﺠﺔ ﻟﺬﻟﻚ ﺳﻮف‬
‫ﻳﻜﻮن ﻟﺪى ﻃﻼب اﻟﻬﻨﺪﺳﺔ اﻻﻟﻜﺘﺮوﻧﻴﺔ، ﻓﻬﻢ اوﻟﻲ وﺗﺠﺎرب ﻋﻤﻠﻴﺔ وﺑﺮاﻋﺔ اآﺎدﻳﻤﻴﺔ ﻓﻲ ﻣﺠﺎل اﻟﺘﺼﻤﻴﻢ واﻟﻤﺤﺎآﺎة‬
‫ﻋﻨﺪ اﻟﺘﺮددات ﻓﺎﺋﻘﺔ اﻟﺴﺮﻋﺔ.‬
‫آﻠﻤﺎت ﻣﻔﺘﺎﺣﻴﺔ: ﺗﺮاﻧﺰﻳﺴﺘﻮر، ﺛﻨﺎﺋﻲ اﻟﻘﻄﺒﻴﺔ، ﻣﻜﺒﺮ ﻋﻤﻠﻴﺎت، ﻣﻨﺨﻔﺾ اﻟﻀﻮﺿﺎء، ﺗﺼﻤﻴﻢ.‬

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