Markus Dietl
ABSTRACT
Traditional PLL architecture uses one control voltage for both integrated and proportional part of the oscillator. Digital PLL architecture uses 2 control words for integrated and proportional part of the oscillator. In this paper, we describe a new architecture of a Phase lock loop which combines the two approaches and takes the advantages of both.
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Index Terms
- A new low power and area efficient semi-digital PLL architecture for low bandwidth applications
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